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| author | Matt Ettus <matt@ettus.com> | 2010-05-27 16:38:01 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-27 16:38:01 -0700 |
| commit | f1e7a07ff6843a0b1d41afb11a7895183329a436 (patch) | |
| tree | 412416f78f48351a4d43bc7aa400b13f06b8d510 /usrp2/models/BUFG.v | |
| parent | d87035457d623fde5b141068f83bb891b7d6978e (diff) | |
| parent | b38d2424b1ac3242146fc9305d9e4ae80e21dede (diff) | |
| download | uhd-f1e7a07ff6843a0b1d41afb11a7895183329a436.tar.gz uhd-f1e7a07ff6843a0b1d41afb11a7895183329a436.tar.bz2 uhd-f1e7a07ff6843a0b1d41afb11a7895183329a436.zip | |
Merge branch 'udp' into u1e_merge_with_udp
* udp:
better test program for just the tx side
fix typo, no functionality difference
ignores
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
reverting logic clean up which should have made timing better, but made it worse instead
Conflicts:
usrp2/control_lib/settings_bus.v
usrp2/top/u2_core/u2_core.v
Diffstat (limited to 'usrp2/models/BUFG.v')
0 files changed, 0 insertions, 0 deletions