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| author | Matt Ettus <matt@ettus.com> | 2010-06-06 02:26:48 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-06-06 02:26:48 -0700 |
| commit | 761e22013c6715987c411216d012098e60684836 (patch) | |
| tree | ba4638c2665e301f4c5839431e287b2fba5920d6 /usrp2/gpmc | |
| parent | 4f1b2441c0250a61f691c038f8bd9cfb229bd103 (diff) | |
| download | uhd-761e22013c6715987c411216d012098e60684836.tar.gz uhd-761e22013c6715987c411216d012098e60684836.tar.bz2 uhd-761e22013c6715987c411216d012098e60684836.zip | |
get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bit
Diffstat (limited to 'usrp2/gpmc')
| -rw-r--r-- | usrp2/gpmc/gpmc_async.v | 5 | ||||
| -rw-r--r-- | usrp2/gpmc/gpmc_sync.v | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 380689c62..f42b835ed 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -82,16 +82,17 @@ module gpmc_async wire [15:0] rx_fifo_space; wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 825d131d8..bac489ca0 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -68,11 +68,12 @@ module gpmc_sync wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space, rx_frame_len; + wire dummy; - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo (.wclk(fifo_clk), .datain(rx18_data), |