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authorMatt Ettus <matt@ettus.com>2010-05-12 18:51:33 -0700
committerMatt Ettus <matt@ettus.com>2010-05-12 18:51:33 -0700
commitb04a1beaab300000ce2d8a5814bd2e37af48286c (patch)
tree980333c397bcd16a5f99278c2cbf3b5be101abe8 /usrp2/gpmc
parented48630974fb8cbdc3b863b13d4e7d7e8fe31434 (diff)
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moved fifos into gpmc_async, reorganized top level a bit, added in crc packet gen and test
Diffstat (limited to 'usrp2/gpmc')
-rw-r--r--usrp2/gpmc/gpmc_async.v91
1 files changed, 53 insertions, 38 deletions
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index dd06478b3..380689c62 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -1,37 +1,38 @@
//////////////////////////////////////////////////////////////////////////////////
module gpmc_async
- (// GPMC signals
- input arst,
- input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
- input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-
- // GPIOs for FIFO signalling
- output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
-
- // Wishbone signals
- input wb_clk, input wb_rst,
- output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
- output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+ #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+ (// GPMC signals
+ input arst,
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+
+ // GPIOs for FIFO signalling
+ output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
+
+ // Wishbone signals
+ input wb_clk, input wb_rst,
+ output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+ output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+
+ // FIFO interface
+ input fifo_clk, input fifo_rst,
+ output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+ input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+
+ input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+
+ output [31:0] debug
+ );
- // FIFO interface
- input fifo_clk, input fifo_rst,
- output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
- input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
- input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+ wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+ wire [15:0] EM_D_fifo;
+ wire [15:0] EM_D_wb;
- output [31:0] debug
- );
-
- wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
- wire [15:0] EM_D_fifo;
- wire [15:0] EM_D_wb;
-
assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
-
- wire bus_error_tx, bus_error_rx;
-
+
+ wire bus_error_tx, bus_error_rx;
+
always @(posedge fifo_clk)
if(fifo_rst)
bus_error <= 0;
@@ -45,9 +46,11 @@ module gpmc_async
// ////////////////////////////////////////////
// TX Data Path
- wire [17:0] tx18_data, tx18b_data;
- wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
- wire [15:0] tx_fifo_space;
+ wire [17:0] tx18_data, tx18b_data;
+ wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+ wire [15:0] tx_fifo_space;
+ wire [35:0] tx36_data;
+ wire tx36_src_rdy, tx36_dst_rdy;
gpmc_to_fifo_async gpmc_to_fifo_async
(.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
@@ -64,18 +67,30 @@ module gpmc_async
fifo19_to_fifo36 f19_to_f36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
- .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+ .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
+ fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+ .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
// ////////////////////////////////////////////
// RX Data Path
-
- wire [17:0] rx18_data, rx18b_data;
- wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
- wire [15:0] rx_fifo_space;
+ wire [17:0] rx18_data, rx18b_data;
+ wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+ wire [15:0] rx_fifo_space;
+ wire [35:0] rx36_data;
+ wire rx36_src_rdy, rx36_dst_rdy;
+
+ fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+ .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
fifo36_to_fifo18 f18_to_f36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+ .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
.f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
@@ -106,6 +121,6 @@ module gpmc_async
.wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
.wb_ack_i(wb_ack_i) );
- assign debug = 0;
+ assign debug = 0;
endmodule // gpmc_async