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authorMatt Ettus <matt@ettus.com>2010-02-25 19:43:01 -0800
committerMatt Ettus <matt@ettus.com>2010-02-25 19:43:01 -0800
commit67dd6732b70c1cd35a7134f4830b09b893255935 (patch)
tree2033576c9e09965558274115691e794c0cef4cad /usrp2/gpmc
parent9143c4a4ca2bf14b43796ae0a0508dbedc40d0e4 (diff)
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gpmc debug pins
Diffstat (limited to 'usrp2/gpmc')
-rw-r--r--usrp2/gpmc/gpmc.v9
1 files changed, 8 insertions, 1 deletions
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 831df3b4c..cf1357232 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -16,7 +16,8 @@ module gpmc
// RAM Interface signals
input ram_clk,
input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done,
- input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done
+ input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done,
+ output [31:0] debug
);
wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
@@ -65,6 +66,12 @@ module gpmc
.read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out),
.write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done));
+
+ assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done},
+ { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done },
+ { 8'd0 },
+ { 8'd0 } };
+
// CS6 is Control, Wishbone bus bridge (wb master)
// Sync version
reg [1:0] cs_del, we_del, oe_del;