progress on synchronous gpmc, but it may not be possible due to the limited number of clock edges

3 files changed, 45 insertions, 43 deletions

diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v
index 647a507b4..ef59d7137 100644
--- a/usrp2/gpmc/fifo_to_gpmc_sync.v
+++ b/usrp2/gpmc/fifo_to_gpmc_sync.v
@@ -6,51 +6,21 @@
 
 module fifo_to_gpmc_sync
   (input arst,
-   input [17:0] data_i, input src_rdy_i, output reg dst_rdy_o,
-   input EM_CLK, inout [15:0] EM_D, input EM_NCS, input EM_NOE,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE,
    output fifo_ready, 
    output reg bus_error);
-   
-   reg [10:0] 	counter;
-   wire 	first_write = (counter == 0);
-   wire 	last_write = ((counter+1) == frame_len);
-   wire 	do_write = ~EM_NCS & ~EM_NWE;
-   
-   always @(posedge EM_CLK or posedge arst)
-     if(arst)
-       data_o <= 0;
-     else if(do_write)
-       begin
-	  data_o[15:0] <= EM_D;
-	  data_o[16] <= first_write;
-	  data_o[17] <= last_write;
-	  //  no byte writes data_o[18] <= |EM_NBE;  // mark half full if either is not enabled  FIXME
-       end
 
-   always @(posedge EM_CLK or posedge arst)
-     if(arst)
-       src_rdy_o <= 0;
-     else if(do_write & ~bus_error)  // Don't put junk in if there is a bus error
-       src_rdy_o <= 1;
-     else
-       src_rdy_o <= 0;    // Assume it was taken, ignore dst_rdy_i
+   assign EM_D = data_i[15:0];
+   wire       read_access = ~EM_NCS & ~EM_NOE;
 
-   always @(posedge EM_CLK or posedge arst)
-     if(arst)
-       counter <= 0;
-     else if(do_write)
-       if(last_write)
-	 counter <= 0;
-       else
-	 counter <= counter + 1;
+   assign dst_rdy_o = read_access;
 
-   assign fifo_ready = first_write & (fifo_space > frame_len);
-   
    always @(posedge EM_CLK or posedge arst)
      if(arst)
        bus_error <= 0;
-     else if(src_rdy_o & ~dst_rdy_i)
+     else if(dst_rdy_o & ~src_rdy_i)
        bus_error <= 1;
-   // must be reset to make the error go away
+   
 
 endmodule // fifo_to_gpmc_sync
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
new file mode 100644
index 000000000..8b8f1abfb
--- /dev/null
+++ b/usrp2/gpmc/fifo_watcher.v
@@ -0,0 +1,26 @@
+
+
+module fifo_watcher
+  (input clk, input reset, input clear,
+   input src_rdy, input dst_rdy, input sof, input eof,
+   output have_packet, output [15:0] length, input next);
+
+   wire   write = src_rdy & dst_rdy & eof;
+   
+   fifo_short #(.WIDTH(16)) frame_lengths
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+      .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) );
+
+   reg [15:0] counter;
+   always @(posedge clk)
+     if(reset | clear)
+       counter <= 1;   // Start at 1
+     else if(src_rdy & dst_rdy)
+       if(eof)
+	 counter <= 1;
+       else
+	 counter <= counter + 1;
+   
+
+endmodule // fifo_watcher
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc_sync.v
index 93308a2d2..41dfeb49e 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc_sync.v
@@ -2,12 +2,12 @@
 
 module gpmc
   (// GPMC signals
+   input arst,
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-   output bus_error,
    
    // GPIOs for FIFO signalling
-   output rx_have_data, output tx_have_space,
+   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
    
    // Wishbone signals
    input wb_clk, input wb_rst,
@@ -28,6 +28,9 @@ module gpmc
 
    assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
 
+   wire 	bus_error_tx, bus_error_rx;
+   assign bus_error = bus_error_tx | bus_error_rx;
+   
    // CS4 is RAM_2PORT for DATA PATH (high-speed data)
    //    Writes go into one RAM, reads come from the other
    // CS6 is for CONTROL PATH (wishbone)
@@ -40,16 +43,15 @@ module gpmc
    wire [15:0] 	tx_fifo_space, tx_frame_len;
    
    assign tx_frame_len = 10;
-   wire 	arst;
    
    gpmc_to_fifo_sync gpmc_to_fifo_sync
      (.arst(arst),
       .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
       .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
       .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
-      .bus_error(bus_error) );
+      .bus_error(bus_error_tx) );
    
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo
      (.wclk(EM_CLK), .datain(tx18_data), 
       .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
       .rclk(fifo_clk), .dataout(tx18b_data), 
@@ -60,7 +62,6 @@ module gpmc
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
       .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
    
-
    // ////////////////////////////////////////////
    // RX Data Path
 
@@ -84,6 +85,11 @@ module gpmc
       .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
       .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
       .fifo_ready(rx_have_data) );
+
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
+      .have_packet(), .length(), .next() );
    
    // ////////////////////////////////////////////
    // Control path on CS6