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| author | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
| commit | d4649caee02a1c76802dc4f8d7d76bb31b14ce09 (patch) | |
| tree | d64c7c7b0496690ac01f865de9b4a7db32c3b7eb /usrp2/gpmc/gpmc.v | |
| parent | b115e4d7661d64c6d20f0421908622b56a91e950 (diff) | |
| download | uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.gz uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.bz2 uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.zip | |
wishbone bridge now with minimal functionality. Need to check
timing and handle wait states.
Diffstat (limited to 'usrp2/gpmc/gpmc.v')
| -rw-r--r-- | usrp2/gpmc/gpmc.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 96ee139fd..1963af6e6 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -18,8 +18,8 @@ module gpmc // CS4 is RAM_2PORT for high-speed data ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); // CS6 is Control, Wishbone bus bridge (wb master) // Sync version |