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authorMatt Ettus <matt@ettus.com>2011-06-12 14:11:05 -0700
committerMatt Ettus <matt@ettus.com>2011-06-12 14:11:05 -0700
commit967637278132513f66be3cd505f77be88ee75691 (patch)
tree6cbabbb6731eec09f9daa006d0a995b30ce08ef6 /usrp2/gpmc/fifo_watcher.v
parentcd9308eb81fd37fcd5142d49c10741f107e6b657 (diff)
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u1e: new write interface, with 2x clock
Diffstat (limited to 'usrp2/gpmc/fifo_watcher.v')
-rw-r--r--usrp2/gpmc/fifo_watcher.v7
1 files changed, 5 insertions, 2 deletions
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
index b139f5143..3971e3c54 100644
--- a/usrp2/gpmc/fifo_watcher.v
+++ b/usrp2/gpmc/fifo_watcher.v
@@ -30,10 +30,11 @@ module fifo_watcher
reg [15:0] counter;
wire [4:0] pkt_count;
assign debug = pkt_count;
+ wire space;
fifo_short #(.WIDTH(16)) frame_lengths
(.clk(clk), .reset(reset), .clear(clear),
- .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+ .datain(counter), .src_rdy_i(write), .dst_rdy_o(space),
.dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read),
.occupied(pkt_count), .space());
@@ -53,7 +54,9 @@ module fifo_watcher
bus_error <= 1;
else if(read & ~have_packet_int)
bus_error <= 1;
-
+ else if(write & ~space)
+ bus_error <= 1;
+
reg in_packet;
always @(posedge clk)
if(reset | clear)