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authorMatt Ettus <matt@ettus.com>2010-04-15 14:56:19 -0700
committerMatt Ettus <matt@ettus.com>2010-04-15 14:56:19 -0700
commit6dd46af16008e46ee8830748194bbc2a1df9fdf3 (patch)
treefe07bd905e821a684d60ea8c413140df28ac08fb /usrp2/gpmc/fifo_watcher.v
parentd7342b46abac60bf4e2811ac4798dc4e06b5844f (diff)
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progress on synchronous gpmc, but it may not be possible due to the limited number of clock edges
Diffstat (limited to 'usrp2/gpmc/fifo_watcher.v')
-rw-r--r--usrp2/gpmc/fifo_watcher.v26
1 files changed, 26 insertions, 0 deletions
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
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+
+
+module fifo_watcher
+ (input clk, input reset, input clear,
+ input src_rdy, input dst_rdy, input sof, input eof,
+ output have_packet, output [15:0] length, input next);
+
+ wire write = src_rdy & dst_rdy & eof;
+
+ fifo_short #(.WIDTH(16)) frame_lengths
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+ .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) );
+
+ reg [15:0] counter;
+ always @(posedge clk)
+ if(reset | clear)
+ counter <= 1; // Start at 1
+ else if(src_rdy & dst_rdy)
+ if(eof)
+ counter <= 1;
+ else
+ counter <= counter + 1;
+
+
+endmodule // fifo_watcher