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authorMatt Ettus <matt@ettus.com>2011-02-25 15:17:31 -0800
committerMatt Ettus <matt@ettus.com>2011-02-25 15:17:31 -0800
commit98a1a03de054306f57be68e1b498c1d39a954472 (patch)
tree1faff6b576e6890a7ead1416296dea587a59d1d0 /usrp2/gpmc/fifo_to_gpmc_async.v
parent87f8f6fca6742a4263b636aa5632f228fccd18f2 (diff)
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fifo36_mux now has shortfifos on the input ports as well as output
Diffstat (limited to 'usrp2/gpmc/fifo_to_gpmc_async.v')
-rw-r--r--usrp2/gpmc/fifo_to_gpmc_async.v5
1 files changed, 0 insertions, 5 deletions
diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
-// Assumes an asynchronous GPMC cycle
-// If a packet bigger or smaller than we are told is sent, behavior is undefined.
-// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-// If there is a bus error, we should be reset
-
module fifo_to_gpmc_async
(input clk, input reset, input clear,
input [17:0] data_i, input src_rdy_i, output dst_rdy_o,