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authorMatt Ettus <matt@ettus.com>2010-11-10 11:29:25 -0800
committerMatt Ettus <matt@ettus.com>2010-11-10 11:29:25 -0800
commitc7be879f6156c219de331df232d1b55ae539f5dd (patch)
treebb2e8012cf7aa54cfc23b4a99e067fd72a5b80e5 /usrp2/gpmc/edge_sync.v
parent98a4130707cf7cad9597b65504211343138391ad (diff)
parent9cd8652b42b5afcba67ef0475e5681b951fe0bdc (diff)
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Merge branch 'u1e' into merge_u1e
* u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
Diffstat (limited to 'usrp2/gpmc/edge_sync.v')
-rw-r--r--usrp2/gpmc/edge_sync.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/usrp2/gpmc/edge_sync.v b/usrp2/gpmc/edge_sync.v
new file mode 100644
index 000000000..5d9417c08
--- /dev/null
+++ b/usrp2/gpmc/edge_sync.v
@@ -0,0 +1,22 @@
+
+
+module edge_sync
+ #(parameter POSEDGE = 1)
+ (input clk,
+ input rst,
+ input sig,
+ output trig);
+
+ reg [1:0] delay;
+
+ always @(posedge clk)
+ if(rst)
+ delay <= 2'b00;
+ else
+ delay <= {delay[0],sig};
+
+ assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10);
+
+endmodule // edge_sync
+
+