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author | Matt Ettus <matt@ettus.com> | 2010-02-25 16:50:09 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-02-25 16:50:09 -0800 |
commit | 030f6a21539207c058b982ffade384ec7a937ec2 (patch) | |
tree | 8432bb4f2536604762a81b1c6847687bb77c2819 /usrp2/gpmc/dbsm.v | |
parent | 0d9c46ae002cad7c144432e86987a81eb33157fc (diff) | |
download | uhd-030f6a21539207c058b982ffade384ec7a937ec2.tar.gz uhd-030f6a21539207c058b982ffade384ec7a937ec2.tar.bz2 uhd-030f6a21539207c058b982ffade384ec7a937ec2.zip |
First cut at passing data buffers around on GPMC bus
Diffstat (limited to 'usrp2/gpmc/dbsm.v')
-rw-r--r-- | usrp2/gpmc/dbsm.v | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..0f27be46a --- /dev/null +++ b/usrp2/gpmc/dbsm.v @@ -0,0 +1,88 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + for(i=0;i<NUM_BUFS;i=i+1) + generate + bsm bsm(.clk(clk), .reset(reset), .clear(clear), + .write_done((write_sel == i) & write_done), + .read_done((read_sel == i) & read_done), + .readable(readable[i]), .writeable(writeable[i])); + endgenerate + + reg full; + + always @(posedge clk) + if(reset | clear) + begin + write_sel <= 0; + full <= 0; + end + else + if(write_done) + if(writeable[write_sel]==(NUM_BUFS-1)) + begin + write_sel <= 0; + if(read_sel == 0) + full <= 1; + end + else + begin + write_sel <= write_sel + 1; + if(read_sel == write_sel + 1) + full <= 1; + end // else: !if(writeable[write_sel]==(NUM_BUFS-1)) + else if(read_done) + full <= 0; + + always @(posedge clk) + if(reset | clear) + read_sel <= 0; + else + if(read_done) + if(readable[read_sel]==(NUM_BUFS-1)) + read_sel <= 0; + else + read_sel <= read_sel + 1; + + assign write_ready = writeable[write_sel]; + assign read_ready = readable[read_sel]; + +endmodule // dbsm |