fpga: xclock fix for edge case condition

1 files changed, 8 insertions, 6 deletions

diff --git a/usrp2/gpmc/cross_clock_reader.v b/usrp2/gpmc/cross_clock_reader.v
index a30e0385f..a8366badc 100644
--- a/usrp2/gpmc/cross_clock_reader.v
+++ b/usrp2/gpmc/cross_clock_reader.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -26,17 +26,19 @@ module cross_clock_reader
         output reg [WIDTH-1:0] out
     );
 
-    reg [WIDTH-1:0] shadow;
+    reg [WIDTH-1:0] shadow0, shadow1;
 
     always @(posedge clk) begin
         if (rst) begin
             out <= DEFAULT;
-            shadow <= DEFAULT;
+            shadow0 <= DEFAULT;
+            shadow1 <= DEFAULT;
         end
-        else if (shadow == in) begin
-            out <= shadow;
+        else if (shadow0 == shadow1) begin
+            out <= shadow1;
         end
-        shadow <= in;
+        shadow0 <= in;
+        shadow1 <= shadow0;
     end
 
 endmodule //cross_clock_reader