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author | Matt Ettus <matt@ettus.com> | 2010-07-01 00:45:20 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:19 -0700 |
commit | 2d67e1453a47a54cf2c9ae651fc7c03d0292ab68 (patch) | |
tree | 8b28dd8fb74f5a8e87f2b888590e0e58bf06d107 /usrp2/gpif/gpif_wr.v | |
parent | 014ea68739c616836bcdfce292c8ab89da26afad (diff) | |
download | uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.tar.gz uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.tar.bz2 uhd-2d67e1453a47a54cf2c9ae651fc7c03d0292ab68.zip |
progress on gpif interface
Diffstat (limited to 'usrp2/gpif/gpif_wr.v')
-rw-r--r-- | usrp2/gpif/gpif_wr.v | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index c5cdc7597..6a73d1721 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -1,11 +1,11 @@ module gpif_wr (input gpif_clk, input gpif_rst, - input [15:0] gpif_data, input WR, + input [15:0] gpif_data, input gpif_wr, output reg have_space, input sys_clk, input sys_rst, - output [19:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, output [31:0] debug ); reg wr_reg; @@ -13,7 +13,7 @@ module gpif_wr always @(posedge gpif_clk) begin - wr_reg <= WR; + wr_reg <= gpif_wr; gpif_data_reg <= gpif_data; end @@ -28,20 +28,28 @@ module gpif_wr write_count <= 0; reg sop; - wire occ = 0; wire eop = (write_count == 255); always @(posedge gpif_clk) - sop <= WR & ~wr_reg; + sop <= gpif_wr & ~wr_reg; wire [15:0] fifo_space; always @(posedge gpif_clk) have_space <= fifo_space > 256; - - fifo_2clock_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo - (.wclk(gpif_clk), .datain({occ,eop,sop,gpif_data_reg}), - .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), - .rclk(sys_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(0), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); + + assign data_o[18] = 0; endmodule // gpif_wr |