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author | Matt Ettus <matt@ettus.com> | 2011-04-16 17:53:09 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:22 -0700 |
commit | 552e81bf1790c531cbbe4087d6ac93f3baab48d4 (patch) | |
tree | 3f55da5da422ada70fbf9433bc860a824365a17f /usrp2/gpif/gpif_rd.v | |
parent | e9a34b8bd51d639e08f31930266e3425de4f53b3 (diff) | |
download | uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.tar.gz uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.tar.bz2 uhd-552e81bf1790c531cbbe4087d6ac93f3baab48d4.zip |
u1p: implement a signal to indicate a partially full usb lut, to flush it
Diffstat (limited to 'usrp2/gpif/gpif_rd.v')
-rw-r--r-- | usrp2/gpif/gpif_rd.v | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index ed0721a36..728b8be78 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -3,6 +3,7 @@ module gpif_rd (input gpif_clk, input gpif_rst, output [15:0] gpif_data, input gpif_rd, input gpif_ep, output reg gpif_empty_d, output reg gpif_empty_c, + output reg gpif_flush, input sys_clk, input sys_rst, input [18:0] data_i, input src_rdy_i, output dst_rdy_o, @@ -10,8 +11,9 @@ module gpif_rd output [31:0] debug ); - wire [17:0] data_o, resp_o; // drop occ bit from input data - wire final_rdy_data, final_rdy_resp; + wire [18:0] data_o; // occ bit indicates flush + wire [17:0] resp_o; // no occ bit + wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix reg [8:0] read_count; @@ -24,10 +26,10 @@ module gpif_rd read_count <= 0; // Data Path - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk - (.wclk(sys_clk), .datain(data_i[17:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); @@ -37,7 +39,7 @@ module gpif_rd wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; - fifo_cascade #(.WIDTH(18), .SIZE(10)) rd_fifo + fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); @@ -56,7 +58,14 @@ module gpif_rd gpif_empty_d <= 1; else gpif_empty_d <= ~|packet_count; - + + // Use occ bit to signal a gpif flush + always @(negedge gpif_clk) + if(gpif_rst) + gpif_flush <= 0; + else if(consume_eop & data_o[18]) + gpif_flush <= ~gpif_flush; + // Response Path wire [15:0] resp_fifolevel; wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; |