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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 16:45:27 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | 39f96a4751e1917a31e940d358399f14d08288fd (patch) | |
| tree | 7b0e8d4261131f4cd31d2e896a3c7e785688813f /usrp2/gpif/gpif_rd.v | |
| parent | 61ace1e0656cd61896e7f457e1d303c2857632c1 (diff) | |
| download | uhd-39f96a4751e1917a31e940d358399f14d08288fd.tar.gz uhd-39f96a4751e1917a31e940d358399f14d08288fd.tar.bz2 uhd-39f96a4751e1917a31e940d358399f14d08288fd.zip | |
u1p: fix bus widths and other warnings
Diffstat (limited to 'usrp2/gpif/gpif_rd.v')
| -rw-r--r-- | usrp2/gpif/gpif_rd.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index c6e503fce..76db72d8a 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -5,12 +5,12 @@ module gpif_rd output reg gpif_empty_d, output reg gpif_empty_c, input sys_clk, input sys_rst, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - input [17:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, output [31:0] debug ); - wire [17:0] data_o, resp_o; + wire [18:0] data_o, resp_o; wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix @@ -24,9 +24,9 @@ module gpif_rd read_count <= 0; // Data Path - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); @@ -34,7 +34,7 @@ module gpif_rd // FIXME -- handle short packets wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; - fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo + fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); @@ -63,7 +63,7 @@ module gpif_rd wire [15:0] resp_fifolevel; wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) resp_fifo_2clk (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), |