diff options
| author | Matt Ettus <matt@ettus.com> | 2011-03-03 16:25:26 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 16:25:26 -0800 |
| commit | 595d341ea6cd9b2207d5443bf79b144f87e9674b (patch) | |
| tree | 2ca121018f1bb5304ac7d6d1c886fbbd805665e5 /usrp2/fifo | |
| parent | caeea5cd11541f1164baa4fc1f6d6e9b474f643e (diff) | |
| download | uhd-595d341ea6cd9b2207d5443bf79b144f87e9674b.tar.gz uhd-595d341ea6cd9b2207d5443bf79b144f87e9674b.tar.bz2 uhd-595d341ea6cd9b2207d5443bf79b144f87e9674b.zip | |
u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdsp
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/packet_router.v | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index bad8fb7fc..61f90d3cf 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -194,21 +194,24 @@ module packet_router wire _combiner0_valid, _combiner1_valid; wire _combiner0_ready, _combiner1_ready; - fifo36_mux _com_output_combiner0( + fifo36_mux #(.prio(0)) // No priority, fair sharing + _com_output_combiner0( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready), - .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready), + .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready), + .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) ); - fifo36_mux _com_output_combiner1( + fifo36_mux #(.prio(0)) // No priority, fair sharing + _com_output_combiner1( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(dsp1_frm_data), .src0_rdy_i(dsp1_frm_valid), .dst0_rdy_o(dsp1_frm_ready), - .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), + .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready), + .data1_i(dsp1_frm_data), .src1_rdy_i(dsp1_frm_valid), .dst1_rdy_o(dsp1_frm_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); - fifo36_mux com_output_source( + fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp + com_output_source( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), |