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| author | Matt Ettus <matt@ettus.com> | 2010-10-06 16:17:13 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-10-06 16:17:13 -0700 |
| commit | 1715dd3cbbe41fff273e5b8a407595903cbd491a (patch) | |
| tree | 956caa54f1945950db78e47f3a8678c53d618733 /usrp2/fifo | |
| parent | 1c3dfe21f8bacbf762b440a23ce652a879288615 (diff) | |
| parent | c07bc03b4f0fe6210f3bfc6ecdc079487d882f7d (diff) | |
| download | uhd-1715dd3cbbe41fff273e5b8a407595903cbd491a.tar.gz uhd-1715dd3cbbe41fff273e5b8a407595903cbd491a.tar.bz2 uhd-1715dd3cbbe41fff273e5b8a407595903cbd491a.zip | |
Merge branch 'ise12' into efifo_merge_dcm
* ise12:
fix timing problem on DAC output bus
clean up DAC inversion and swapping to match schematics
Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
Diffstat (limited to 'usrp2/fifo')
0 files changed, 0 insertions, 0 deletions