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| author | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
| commit | 8a49d85f0b26a0ab459d41831dc2b03c91744458 (patch) | |
| tree | 95b6686d273102858c47efbb3b569daa14feac7e /usrp2/fifo | |
| parent | 354b55e52ed4edd4f417e7cb28b93960bebaf762 (diff) | |
| download | uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.gz uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.bz2 uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.zip | |
u2/u2p: moved dsp framer into vita_rx_chain
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/packet_router.v | 28 |
1 files changed, 5 insertions, 23 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index e10a8f23d..edaa506b1 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -69,6 +69,8 @@ module packet_router //setting register for mode control wire [31:0] _sreg_mode_ctrl; + wire master_mode_flag; + setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), @@ -179,16 +181,11 @@ module packet_router //////////////////////////////////////////////////////////////////// // Communication output source combiner (feeds UDP proto machine) - // - DSP framer + // - DSP input // - CPU input // - ERR input //////////////////////////////////////////////////////////////////// - //streaming signals from the dsp framer to the combiner - wire [35:0] dsp0_frm_data, dsp1_frm_data; - wire dsp0_frm_valid, dsp1_frm_valid; - wire dsp0_frm_ready, dsp1_frm_ready; - //dummy signals to join the the muxes below wire [35:0] _combiner0_data, _combiner1_data; wire _combiner0_valid, _combiner1_valid; @@ -205,8 +202,8 @@ module packet_router fifo36_mux #(.prio(0)) // No priority, fair sharing _com_output_combiner1( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready), - .data1_i(dsp1_frm_data), .src1_rdy_i(dsp1_frm_valid), .dst1_rdy_o(dsp1_frm_ready), + .data0_i(dsp0_inp_data), .src0_rdy_i(dsp0_inp_valid), .dst0_rdy_o(dsp0_inp_ready), + .data1_i(dsp1_inp_data), .src1_rdy_i(dsp1_inp_valid), .dst1_rdy_o(dsp1_inp_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); @@ -462,21 +459,6 @@ module packet_router ); //////////////////////////////////////////////////////////////////// - // DSP input framer - //////////////////////////////////////////////////////////////////// - dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(0)) dsp0_framer36( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data_i(dsp0_inp_data), .src_rdy_i(dsp0_inp_valid), .dst_rdy_o(dsp0_inp_ready), - .data_o(dsp0_frm_data), .src_rdy_o(dsp0_frm_valid), .dst_rdy_i(dsp0_frm_ready) - ); - - dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(2)) dsp1_framer36( - .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data_i(dsp1_inp_data), .src_rdy_i(dsp1_inp_valid), .dst_rdy_o(dsp1_inp_ready), - .data_o(dsp1_frm_data), .src_rdy_o(dsp1_frm_valid), .dst_rdy_i(dsp1_frm_ready) - ); - - //////////////////////////////////////////////////////////////////// // UDP TX Protocol machine //////////////////////////////////////////////////////////////////// |