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authorJosh Blum <josh@joshknows.com>2010-11-21 13:24:48 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 19:06:59 -0800
commit257ba8bb1caebca29e1dddd9e73bfd32abe8d1d1 (patch)
treecad9f7ee535fa439fde9efa9746ec326f72f170f /usrp2/fifo
parent15180da94ec11958ad97aaf0e79c29e2081b8b51 (diff)
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packet_router: added a way to program in the ip and mac addrs, and added inspector check
Diffstat (limited to 'usrp2/fifo')
-rw-r--r--usrp2/fifo/packet_router.v19
1 files changed, 17 insertions, 2 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index dda1519b8..7bc5255be 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -74,6 +74,8 @@ module packet_router
reg master_mode_flag;
reg router_clr;
reg [BUF_SIZE-1:0] cpu_inp_line_count;
+ reg [31:0] my_ip_addr;
+ reg [47:0] my_mac_addr;
always @(posedge control_changed) begin
cpu_out_hs_ctrl <= control[0];
@@ -81,6 +83,18 @@ module packet_router
master_mode_flag <= control[2];
router_clr <= control[8];
cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16];
+ case (control[6:4])
+ 3'b001:
+ my_ip_addr[15:0] <= control[31:16];
+ 3'b010:
+ my_ip_addr[31:16] <= control[31:16];
+ 3'b011:
+ my_mac_addr[15:0] <= control[31:16];
+ 3'b100:
+ my_mac_addr[31:16] <= control[31:16];
+ 3'b101:
+ my_mac_addr[47:32] <= control[31:16];
+ endcase
end
wire cpu_out_hs_stat;
@@ -362,8 +376,9 @@ module packet_router
&& (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero
;
- wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & 1'b1; //TODO check for ip match
- wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & 1'b0; //TODO check for ip mismatch
+ wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0;
+ wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & com_inp_dregs_my_ip_match;
+ wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & ~com_inp_dregs_my_ip_match;
//Inspector output flags special case:
//Inject SOF into flags at first DSP line.