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author | Matt Ettus <matt@ettus.com> | 2011-05-09 14:58:30 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-09 14:58:30 -0700 |
commit | d8aae182ffdafdd61bbd0100f845d7c93e6ec591 (patch) | |
tree | 356eba18476f8165367a9bc3585c9df9b44680e1 /usrp2/fifo | |
parent | d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4 (diff) | |
download | uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.tar.gz uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.tar.bz2 uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.zip |
u1e: get dsp_framer36 from u1p so it can skip the protocol header
Diffstat (limited to 'usrp2/fifo')
-rw-r--r-- | usrp2/fifo/dsp_framer36.v | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index c2ae8f96c..58455cee1 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -1,9 +1,13 @@ -// Frame DSP packets with a header line to be handled by the protocol machine +// This has 3 functions: +// Correct the VITA packet length +// [optional] Frame DSP packets with an header line to be handled by the protocol machine +// Hold on to the packet until there is a complete one before allowing to leave module dsp_framer36 #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0) + parameter PORT_SEL = 0, + parameter PROT_ENG_FLAGS = 1) (input clk, input reset, input clear, input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); @@ -48,10 +52,10 @@ module dsp_framer36 always @(posedge clk) if(reset | clear) - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else if(do_xfer_out) if(dfifo_out_data[33]) // eof - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else pkt_len_out <= pkt_len_out + 1; @@ -59,8 +63,8 @@ module dsp_framer36 wire [1:0] port_sel_bits = PORT_SEL; - assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : + assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : + (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; |