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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 11:29:15 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 11:29:15 -0800 |
| commit | 173f03d981bacb746a865ca661c265e0e45ec3b1 (patch) | |
| tree | afe07cfe3ab723db257bc7a259c5efed87205fec /usrp2/fifo | |
| parent | 6a8f7025044dd002fa1242cc10da536f1d6ad007 (diff) | |
| parent | 1745009767ceb72e5cba6f4bfc8517ef33fecdf6 (diff) | |
| download | uhd-173f03d981bacb746a865ca661c265e0e45ec3b1.tar.gz uhd-173f03d981bacb746a865ca661c265e0e45ec3b1.tar.bz2 uhd-173f03d981bacb746a865ca661c265e0e45ec3b1.zip | |
Merge branch 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv into ethfifo_reorg
* 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv:
ethfifo_reorg: switch buffer int2 lastline to work as a length parameter
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/buffer_int2.v | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v index 765b125fb..c73456b74 100644 --- a/usrp2/fifo/buffer_int2.v +++ b/usrp2/fifo/buffer_int2.v @@ -32,12 +32,13 @@ module buffer_int2 ); reg [BUF_SIZE-1:0] rd_addr, wr_addr; + wire [BUF_SIZE-1:0] rd_addr_next = rd_addr + 1; wire [31:0] ctrl; wire wr_done, wr_error, wr_idle; wire rd_done, rd_error, rd_idle; wire we, en, go; - reg [BUF_SIZE-1:0] lastline; + reg [BUF_SIZE-1:0] rd_length; wire read = ctrl[3]; wire rd_clear = ctrl[2]; wire write = ctrl[1]; @@ -72,13 +73,13 @@ module buffer_int2 begin rd_addr <= 0; rd_state <= PRE_READ; - lastline <= ctrl[15+BUF_SIZE:16]; + rd_length <= ctrl[15+BUF_SIZE:16]; end PRE_READ : begin rd_state <= READING; - rd_addr <= rd_addr + 1; + rd_addr <= rd_addr_next; rd_occ <= 2'b00; rd_sop <= 1; rd_eop <= 0; @@ -88,8 +89,8 @@ module buffer_int2 if(rd_ready_i) begin rd_sop <= 0; - rd_addr <= rd_addr + 1; - if(rd_addr == lastline) + rd_addr <= rd_addr_next; + if(rd_addr_next == rd_length) begin rd_eop <= 1; // FIXME assign occ here |