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| author | Matt Ettus <matt@ettus.com> | 2010-10-08 16:01:42 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 18:07:07 -0800 |
| commit | 336afd8b8bb6a655b6297f86cffc05d8e46d1a4a (patch) | |
| tree | e0f68d5de4cd8f0a9dd15a41684e3676419a27e8 /usrp2/fifo | |
| parent | c868b37abecb9676a7efcc5072e4c0938e442905 (diff) | |
| download | uhd-336afd8b8bb6a655b6297f86cffc05d8e46d1a4a.tar.gz uhd-336afd8b8bb6a655b6297f86cffc05d8e46d1a4a.tar.bz2 uhd-336afd8b8bb6a655b6297f86cffc05d8e46d1a4a.zip | |
add a fifo to the end of the mux to help in timing.
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/fifo36_mux.v | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 92bf13ff9..c6fd40f27 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -20,6 +20,9 @@ module fifo36_mux wire eof0 = data0_i[33]; wire eof1 = data1_i[33]; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + always @(posedge clk) if(reset | clear) state <= MUX_IDLE0; @@ -32,7 +35,7 @@ module fifo36_mux state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_i & eof0) + if(src0_rdy_i & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : @@ -42,16 +45,20 @@ module fifo36_mux state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_i & eof1) + if(src1_rdy_i & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; - assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; + assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + fifo_short #(.WIDTH(36)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); endmodule // fifo36_demux |