Merge branch 'gpmc_testing' into ethfifo_reorg

* gpmc_testing:
  timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity.
  correct port names
  fifo36_mux now has shortfifos on the input ports as well as output
  timed tester : Bring out src/dst flags for rx chain for testing.
  u1e: hook up tester controls
  move declarations to before use
  hook up under/overruns for debug purposes
  e100: integrate loopback and timed testing into main image
  Fix endianess for packet length and sequence number for e100 timed image.
  put these files in the right place.  newfifo is long gone.

1 files changed, 29 insertions, 0 deletions

diff --git a/usrp2/fifo/packet_tb.v b/usrp2/fifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/usrp2/fifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb