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| author | Josh Blum <josh@joshknows.com> | 2010-12-12 17:48:58 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-12 17:48:58 -0800 |
| commit | 6c1d4ebdbd2229654976dd672a5433c300dc0d17 (patch) | |
| tree | 246437fa0609a5b52f5906493e03e077eb7fec24 /usrp2/fifo/packet_router.v | |
| parent | 04f391a2948c07ff1fed9f02497c85cf0f098fee (diff) | |
| download | uhd-6c1d4ebdbd2229654976dd672a5433c300dc0d17.tar.gz uhd-6c1d4ebdbd2229654976dd672a5433c300dc0d17.tar.bz2 uhd-6c1d4ebdbd2229654976dd672a5433c300dc0d17.zip | |
packet_router: harmless logic tweaks
Diffstat (limited to 'usrp2/fifo/packet_router.v')
| -rw-r--r-- | usrp2/fifo/packet_router.v | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 5118c69b3..9491d4346 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -253,13 +253,10 @@ module packet_router assign cpu_out_line_count = cpu_out_addr; wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; - wire cpu_out_reading = ( + assign cpu_out_ready = ( cpu_out_state == CPU_OUT_STATE_WAIT_SOF || cpu_out_state == CPU_OUT_STATE_WAIT_EOF )? 1'b1 : 1'b0; - - wire cpu_out_we = cpu_out_reading; - assign cpu_out_ready = cpu_out_reading; assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; RAMB16_S36_S36 cpu_out_buff( @@ -267,8 +264,8 @@ module packet_router .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface to CPU (input only) - .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0), - .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we) + .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data[31:0]),.DIPB(4'h0), + .ENB(cpu_out_ready & cpu_out_valid),.SSRB(0),.WEB(cpu_out_ready & cpu_out_valid) ); always @(posedge stream_clk) |