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authorMatt Ettus <matt@ettus.com>2011-02-16 17:04:30 -0800
committerMatt Ettus <matt@ettus.com>2011-02-16 17:04:30 -0800
commit57f956af2f9cc3463970e8d47c2f59ec549accbf (patch)
treea1928ee8959c8c9a7173b35e188951a676ac2da6 /usrp2/fifo/packet_generator32.v
parent4c377e12d56be4afa78b0f83dd8546b59ec837f2 (diff)
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e100: integrate loopback and timed testing into main image
Diffstat (limited to 'usrp2/fifo/packet_generator32.v')
-rw-r--r--usrp2/fifo/packet_generator32.v2
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/fifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v
index 6f8004964..1dc57191d 100644
--- a/usrp2/fifo/packet_generator32.v
+++ b/usrp2/fifo/packet_generator32.v
@@ -2,6 +2,7 @@
module packet_generator32
(input clk, input reset, input clear,
+ input [127:0] header,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
wire [7:0] ll_data;
@@ -10,6 +11,7 @@ module packet_generator32
packet_generator pkt_gen
(.clk(clk), .reset(reset), .clear(clear),
.data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+ .header(header),
.src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
ll8_to_fifo36 ll8_to_f36