Matt's attempt at merging

Merge branch 'tx_policy' into ise12_efifo_work

* tx_policy:
  rx error context packets should not be marked as errors in the fifo
  provide a way to get out of the error state without processor intervention
  sequence number reset upon programming streamid
  attempt at avoiding infinite error messages
  implemented "next packet" and "next burst" policies
  sequence errors can happen on start of burst as well.
  more informative error codes
  cleaner error handling
  introduce new error types
  test mux and gen_context_pkt
  this is an output file, it shouldn't be checked in
  insert protocol engine flags when requested
  move the streamid so it isn't at the same address as clear_state
  connect the demux
  fix a typo
  tx error packets now muxed into the ethernet stream back to the host
  checkpoint.  New context packet generator to report underruns and other errors

Conflicts:
	usrp2/top/u2_rev3/u2_core_udp.v

1 files changed, 0 insertions, 5506 deletions

diff --git a/usrp2/fifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd
deleted file mode 100644
index 796889e7d..000000000
--- a/usrp2/fifo/fifo_new_tb.vcd
+++ /dev/null
@@ -1,5506 +0,0 @@
-$date
-	Thu Mar 19 17:21:11 2009
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1ps
-$end
-$scope module fifo_new_tb $end
-$var wire 1 ! dst_rdy_f36i $end
-$var wire 36 " f36_in [35:0] $end
-$var wire 36 # i1 [35:0] $end
-$var wire 1 $ i1_dr $end
-$var wire 1 % i1_sr $end
-$var wire 19 & i2 [18:0] $end
-$var wire 1 ' i2_dr $end
-$var wire 1 ( i2_sr $end
-$var wire 19 ) i3 [18:0] $end
-$var wire 1 * i3_dr $end
-$var wire 1 + i3_sr $end
-$var wire 36 , i4 [35:0] $end
-$var wire 1 - i4_sr $end
-$var wire 8 . ll_data [7:0] $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 2 ll_src_rdy_n $end
-$var reg 1 3 clear $end
-$var reg 1 4 clk $end
-$var reg 16 5 count [15:0] $end
-$var reg 1 6 dst_rdy_f36o $end
-$var reg 32 7 f36_data [31:0] $end
-$var reg 1 8 f36_eof $end
-$var reg 2 9 f36_occ [1:0] $end
-$var reg 1 : f36_sof $end
-$var reg 1 ; i4_dr $end
-$var reg 1 < rst $end
-$var reg 1 = src_rdy_f36i $end
-$scope module fifo_short1 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 36 @ datain [35:0] $end
-$var wire 36 A dataout [35:0] $end
-$var wire 1 $ dst_rdy_i $end
-$var wire 1 ! dst_rdy_o $end
-$var wire 1 B read $end
-$var wire 1 C reset $end
-$var wire 1 D src_rdy_i $end
-$var wire 1 % src_rdy_o $end
-$var wire 1 E write $end
-$var reg 4 F a [3:0] $end
-$var reg 1 G empty $end
-$var reg 1 H full $end
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-$enddefinitions $end
-#0
-$dumpvars
-bx \$
-bx [$
-bx Z$
-xY$
-xX$
-xW$
-bx V$
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-0T$
-0S$
-b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$
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-xG$
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-x@$
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-x>$
-x=$
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-x;$
-x:$
-x9$
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-bx /$
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-b0 ,$
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-0*$
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