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author | Matt Ettus <matt@ettus.com> | 2010-06-14 13:23:18 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-06-14 13:23:18 -0700 |
commit | a97707caa8e9f19fdc81061ac11a73f41aab2704 (patch) | |
tree | c75983a4caff316fe1c64cdba047229ac4584cc7 /usrp2/fifo/fifo_cascade.v | |
parent | a4b11332ab4f6a24bf4645c0b2770f9578a36f45 (diff) | |
parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
download | uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.tar.gz uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.tar.bz2 uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.zip |
Merge branch 'master' into u1e_newbuild
Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
Diffstat (limited to 'usrp2/fifo/fifo_cascade.v')
-rw-r--r-- | usrp2/fifo/fifo_cascade.v | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v new file mode 100644 index 000000000..fdd8449bc --- /dev/null +++ b/usrp2/fifo/fifo_cascade.v @@ -0,0 +1,52 @@ + + +// This FIFO exists to provide an intermediate point for the data on its +// long trek from one RAM (in the buffer pool) to another (in the longfifo) +// The shortfifo is more flexible in its placement since it is based on +// distributed RAM + +// This one has the shortfifo on both the in and out sides. +module fifo_cascade + #(parameter WIDTH=32, SIZE=9) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + output [15:0] space, + output [15:0] occupied); + + wire [WIDTH-1:0] data_int, data_int2; + wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2; + + wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; + wire [15:0] l_space, l_occupied; + + fifo_short #(.WIDTH(WIDTH)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1), + .space(s1_space),.occupied(s1_occupied) ); + + fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1), + .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2), + .space(l_space),.occupied(l_occupied) ); + + fifo_short #(.WIDTH(WIDTH)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(s2_space),.occupied(s2_occupied) ); + + assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space; + assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied; + +endmodule // cascadefifo2 + + + + |