External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code.

Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.

1 files changed, 4 insertions, 4 deletions

diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v
index fdd8449bc..ff2993ed5 100644
--- a/usrp2/fifo/fifo_cascade.v
+++ b/usrp2/fifo/fifo_cascade.v
@@ -10,11 +10,11 @@ module fifo_cascade
   #(parameter WIDTH=32, SIZE=9)
     (input clk, input reset, input clear,
      input [WIDTH-1:0] datain,
-     input src_rdy_i,
-     output dst_rdy_o,
+     input src_rdy_i,                // WRITE
+     output dst_rdy_o,               // not FULL
      output [WIDTH-1:0] dataout,
-     output src_rdy_o,
-     input dst_rdy_i,
+     output src_rdy_o,               // not EMPTY
+     input dst_rdy_i,                // READ
      output [15:0] space,
      output [15:0] occupied);