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| author | Ian Buckley <ianb@server2.(none)> | 2010-08-12 14:35:06 -0700 |
|---|---|---|
| committer | Ian Buckley <ianb@server2.(none)> | 2010-08-12 14:35:06 -0700 |
| commit | bbe1965c18bb97d4a4d7b3cde1c343d147c23278 (patch) | |
| tree | 2e1044203eccd92d1fc8c48261cbea539ad41a0e /usrp2/fifo/fifo_cascade.v | |
| parent | 030d98cef5133072ca53dddbb62669c57810c387 (diff) | |
| download | uhd-bbe1965c18bb97d4a4d7b3cde1c343d147c23278.tar.gz uhd-bbe1965c18bb97d4a4d7b3cde1c343d147c23278.tar.bz2 uhd-bbe1965c18bb97d4a4d7b3cde1c343d147c23278.zip | |
Regenerated FIFO's for extfifo.
There are problems with certain configurations it seems.
It is important that the fifo_xlnx_512x36_2clk_18to36 is
generated with the "almost_full" pin even though it is not used
in the application. if this pin is omitted the FPGA image doesn't
work correctly
Diffstat (limited to 'usrp2/fifo/fifo_cascade.v')
0 files changed, 0 insertions, 0 deletions