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authorMatt Ettus <matt@ettus.com>2010-08-25 18:47:34 -0700
committerMatt Ettus <matt@ettus.com>2010-08-25 18:47:34 -0700
commit32d06cadd5c60e1080e6124cfd46c44a97157adf (patch)
tree4337273f0beba96f15dac6560fcc72f396f1fdef /usrp2/fifo/fifo36_mux.v
parent02c2a3fd08b1ae1a306fa45d89b55dafeaffb508 (diff)
parent743ea16da4eef07cf9956f4098fc4b959e689c00 (diff)
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Merge branch 'u1e_merge' into u1e
* u1e_merge: no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy
Diffstat (limited to 'usrp2/fifo/fifo36_mux.v')
-rw-r--r--usrp2/fifo/fifo36_mux.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index 04ec5abe8..92bf13ff9 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -52,6 +52,6 @@ module fifo36_mux
assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
- assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i;
+ assign data_o = (state==MUX_DATA0) ? data0_i : data1_i;
endmodule // fifo36_demux