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author | Matt Ettus <matt@ettus.com> | 2010-08-16 15:20:55 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-08-16 15:20:55 -0700 |
commit | 02998fa22b62601a98ed65858bfe184103f796fb (patch) | |
tree | 9deb819addabcefdc820061cd80670dacc779648 /usrp2/fifo/fifo36_mux.v | |
parent | 9ff71ccb960f71384f293dcb97fb2841d1805fa3 (diff) | |
parent | c4ae87f3554753877a35cab3b86cbf267fb2c035 (diff) | |
download | uhd-02998fa22b62601a98ed65858bfe184103f796fb.tar.gz uhd-02998fa22b62601a98ed65858bfe184103f796fb.tar.bz2 uhd-02998fa22b62601a98ed65858bfe184103f796fb.zip |
Matt's attempt at merging
Merge branch 'tx_policy' into ise12_efifo_work
* tx_policy:
rx error context packets should not be marked as errors in the fifo
provide a way to get out of the error state without processor intervention
sequence number reset upon programming streamid
attempt at avoiding infinite error messages
implemented "next packet" and "next burst" policies
sequence errors can happen on start of burst as well.
more informative error codes
cleaner error handling
introduce new error types
test mux and gen_context_pkt
this is an output file, it shouldn't be checked in
insert protocol engine flags when requested
move the streamid so it isn't at the same address as clear_state
connect the demux
fix a typo
tx error packets now muxed into the ethernet stream back to the host
checkpoint. New context packet generator to report underruns and other errors
Conflicts:
usrp2/top/u2_rev3/u2_core_udp.v
Diffstat (limited to 'usrp2/fifo/fifo36_mux.v')
-rw-r--r-- | usrp2/fifo/fifo36_mux.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 04ec5abe8..92bf13ff9 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -52,6 +52,6 @@ module fifo36_mux assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i; + assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; endmodule // fifo36_demux |