Merge branch 'u1e' into merge_u1e

* u1e: (130 commits)
  invert led signals because they are active low
  duh
  allow for CS to rise before, at the same time, or after OE
  better debug pins
  watch the ethernet chip select on our debug bus
  fix timing issue on DAC outputs with rev 2.  This puts the whole system on a 90 degree phase shift
  send all gpmc signals to mictor
  updated pins to match rev2, removed dip switch, etc.  seems to compile ok.
  pins are different on rev2
  fixed makefile to compile with our new system
  add register to tell host about compatibility level and which image we are using
  move declaration to make loopback compile
  no need for protocol headers since we're not doing ethernet
  match the signal names in this design
  debug pins cleanup
  properly integrate the new tx chain
  catch up with tx_policy
  attach run_tx and run_rx to leds
  connect atr
  delay the q channel to make the channels line up on the AD9862
  ...

Conflicts:
	usrp2/control_lib/Makefile.srcs

1 files changed, 23 insertions, 17 deletions

diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v
index 5f9aeff9b..0e6bcea68 100644
--- a/usrp2/fifo/fifo19_to_fifo36.v
+++ b/usrp2/fifo/fifo19_to_fifo36.v
@@ -1,26 +1,31 @@
 
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
 module fifo19_to_fifo36
-  (input clk, input reset, input clear,
-   input [18:0] f19_datain,
-   input f19_src_rdy_i,
-   output f19_dst_rdy_o,
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [18:0] f19_datain,
+    input f19_src_rdy_i,
+    output f19_dst_rdy_o,
 
-   output [35:0] f36_dataout,
-   output f36_src_rdy_o,
-   input f36_dst_rdy_i,
-   output [31:0] debug
-   );
+    output [35:0] f36_dataout,
+    output f36_src_rdy_o,
+    input f36_dst_rdy_i,
+    output [31:0] debug
+    );
 
-   reg 	 f36_sof, f36_eof, f36_occ;
+   reg 		  f36_sof, f36_eof, f36_occ;
    
-   reg [1:0] state;
-   reg [15:0] dat0, dat1;
+   reg [1:0] 	  state;
+   reg [15:0] 	  dat0, dat1;
 
-   wire f19_sof  = f19_datain[16];
-   wire f19_eof  = f19_datain[17];
-   wire f19_occ  = f19_datain[18];
+   wire 	  f19_sof  = f19_datain[16];
+   wire 	  f19_eof  = f19_datain[17];
+   wire 	  f19_occ  = f19_datain[18];
 
-   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+   wire 	  xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
 
    always @(posedge clk)
      if(f19_src_rdy_i & ((state==0)|xfer_out))
@@ -68,7 +73,8 @@ module fifo19_to_fifo36
        dat0 		   <= f19_datain;
    
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
-   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_dataout    = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
+			      {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
 
    assign    debug = state;