Found bug due to not accounting for the correct number of possible in flight READ operations that can be in the extfifo pipeline.

Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept
in flight read data upon completion.
Had to generate the FIFO using Coregen  from ISE12.1 due to 10.1 verion not working correctly in FPGA
Still have to tackle making this simulate in Icarus

3 files changed, 60 insertions, 10 deletions

diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index a506d71e2..c7e8f6cfb 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -57,10 +57,18 @@ module ext_fifo
 								 .dout(write_data), // Bus [17 : 0] 
 								 .full(full1),			
 							         .empty(empty1));
-   assign 	    dst_rdy_o = ~full1;
+
+    assign 	    dst_rdy_o = ~full1;
+   
+/* -----\/----- EXCLUDED -----\/-----
+   assign 	    space_avail = ~full2;
+   assign 	    data_avail = ~empty1;
+   assign 	    read_data = write_data;
+ -----/\----- EXCLUDED -----/\----- */
+   
 
    // External FIFO running at ext clock rate  and 18 bit width.
-   nobl_fifo  #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH))
+   nobl_fifo  #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH))
      nobl_fifo_i1
        (   
 	   .clk(ext_clk),
@@ -94,7 +102,8 @@ module ext_fifo
 								 .rd_en(dst_rdy_i),
 								 .dout(dataout), // Bus [35 : 0]
 								 .full(full2),
-								 .almost_full(almost_full2),
+								 .almost_full(),
+								 .prog_full(almost_full2),
 								 .empty(empty2));
    assign  src_rdy_o = ~empty2;
 
diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v
index 38df4a285..a93d524d5 100644
--- a/usrp2/extramfifo/ext_fifo_tb.v
+++ b/usrp2/extramfifo/ext_fifo_tb.v
@@ -51,6 +51,44 @@ module ext_fifo_tb();
    always
      #4 ext_clk <= ~ext_clk;
 
+   initial
+     begin
+	rst <= 1;
+	repeat (5) @(negedge int_clk);
+	rst <= 0;
+	@(negedge int_clk);
+	while (datain < 10000)
+	  begin
+	     @(negedge int_clk);
+	     datain <= datain + dst_rdy_o;
+	     src_rdy_i <= dst_rdy_o;
+	  end
+     end // initial begin
+
+   
+   initial
+     begin
+	repeat (20) @(negedge int_clk);
+	  
+	// Fall through fifo, first output already valid
+	if (dataout !== ref_dataout)
+	  $display("Error: Expected %x, got %x",ref_dataout, dataout);
+	
+	while (ref_dataout < 10000)
+	  begin
+	     @(negedge int_clk);
+	     ref_dataout <= ref_dataout + src_rdy_o ;
+	     dst_rdy_i <= src_rdy_o;
+	     if ((dataout !== ref_dataout) && src_rdy_o)
+	       $display("Error: Expected %x, got %x",ref_dataout, dataout);
+	     @(negedge int_clk);
+	     dst_rdy_i <= 0;
+	     repeat(6) @(negedge int_clk);
+	  end
+     end
+   
+
+/* -----\/----- EXCLUDED -----\/-----
  
    initial
      begin
@@ -112,6 +150,7 @@ module ext_fifo_tb();
      end // initial begin
 
 
+ -----/\----- EXCLUDED -----/\----- */
    ///////////////////////////////////////////////////////////////////////////////////
    // Simulation control                                                            //
    ///////////////////////////////////////////////////////////////////////////////////
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v
index 7ddb517c7..03e3f5223 100644
--- a/usrp2/extramfifo/nobl_fifo.v
+++ b/usrp2/extramfifo/nobl_fifo.v
@@ -5,7 +5,7 @@
 // "full" and "empty" flags.
 
 module nobl_fifo
-  #(parameter WIDTH=18,DEPTH=19)
+  #(parameter WIDTH=18,DEPTH=19,FDEPTH=10)
     (   
 	input clk,
 	input rst,
@@ -27,9 +27,9 @@ module nobl_fifo
 	input upstream_full // (Connect to almost full flag upstream)
 	);
 
-   reg [DEPTH-1:0] capacity;
-   reg [DEPTH-1:0] wr_pointer;
-   reg [DEPTH-1:0] rd_pointer;
+   reg [FDEPTH-1:0] capacity;
+   reg [FDEPTH-1:0] wr_pointer;
+   reg [FDEPTH-1:0] rd_pointer;
    wire [DEPTH-1:0] address;
    reg 		   supress;
    reg 		   data_avail_int;   // Data available with high latency from ext FIFO flag
@@ -51,7 +51,7 @@ module nobl_fifo
    always @(posedge clk)
      if (rst)
        begin
-	  capacity <= 1 << (DEPTH-1);
+	  capacity <= 1 << (FDEPTH-1);
 	  wr_pointer <= 0;
 	  rd_pointer <= 0;
 	  space_avail <= 0;
@@ -60,9 +60,11 @@ module nobl_fifo
        end
      else	  
        begin
-	  space_avail <= ~((capacity == 0) || (read&&write) || (capacity == 1 && write) );
+	  // No space available if:
+	  // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision)
+	  space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );
 	  // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO.
-	  data_avail_int <= ~((capacity == (1 << (DEPTH-1))) || (read&&write)  || (capacity == ((1 << (DEPTH-1))-1) && read)  );
+	  data_avail_int <= ~((capacity == (1 << (FDEPTH-1))) || (read&&write)  || ((capacity == ((1 << (FDEPTH-1))-1)) && read)  );
 	  supress <= read && write;
 	  wr_pointer <= wr_pointer + write;
 	  rd_pointer <= rd_pointer + ((~write && read) || supress);