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authorIan Buckley <ianb@server2.(none)>2010-09-01 00:45:40 -0700
committerIan Buckley <ianb@server2.(none)>2010-09-01 00:45:40 -0700
commit09c0420f9068187e5e4146254c7ea769b9c69186 (patch)
tree4e7a367e73e9f923f94c305abfcba760a3cd47f4 /usrp2/extramfifo/nobl_if.v
parentf18bf439ad1456452532285eedd131c54065213c (diff)
parent596fc8d80ed2200f6d4bb597cb7185b63cf0be77 (diff)
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Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into efifo_merge
Diffstat (limited to 'usrp2/extramfifo/nobl_if.v')
-rw-r--r--usrp2/extramfifo/nobl_if.v12
1 files changed, 8 insertions, 4 deletions
diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 24d463b1e..391a841e8 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -9,11 +9,11 @@ module nobl_if
output [WIDTH-1:0] RAM_D_po,
output reg RAM_D_poe,
output [DEPTH-1:0] RAM_A,
- output RAM_WEn,
+ output reg RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
- output RAM_CE1n,
+ output reg RAM_CE1n,
input [DEPTH-1:0] address,
input [WIDTH-1:0] data_out,
output reg [WIDTH-1:0] data_in,
@@ -54,11 +54,15 @@ module nobl_if
else
begin
enable_pipe1 <= enable;
+ RAM_CE1n <= ~enable; // Creates IOB flob
+
if (enable)
begin
address_pipe1 <= address;
write_pipe1 <= write;
+ RAM_WEn <= ~write; // Creates IOB flob
+
if (write)
data_out_pipe1 <= data_out;
@@ -68,8 +72,8 @@ module nobl_if
// Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
assign RAM_A = address_pipe1;
assign RAM_CENn = 1'b0;
- assign RAM_WEn = ~write_pipe1;
- assign RAM_CE1n = ~enable_pipe1;
+ // assign RAM_WEn = ~write_pipe1;
+// assign RAM_CE1n = ~enable_pipe1;
//
// Pipeline stage2