External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code.

Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.

1 files changed, 4 insertions, 5 deletions

diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 3143ce5ba..24d463b1e 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -1,3 +1,5 @@
+// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
+
 module nobl_if
   #(parameter WIDTH=18,DEPTH=19)  
     (
@@ -35,9 +37,9 @@ module nobl_if
    reg [WIDTH-1:0] data_out_pipe3;
 
    assign 	   RAM_LDn = 0;
+   // ZBT/NoBL RAM actually manages its own output enables very well.
    assign 	   RAM_OEn = 0;
    
-
    //
    // Pipeline stage 1
    //
@@ -129,8 +131,5 @@ module nobl_if
 	  else
 	    data_in_valid <= 1'b0;
        end // always @ (posedge clk)
-   
-   
-   
-   
+     
 endmodule // nobl_if