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| author | Ian Buckley <ian.buckley@gmail.com> | 2010-10-15 11:37:23 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:35 -0800 |
| commit | 7e75951d263c00e9f84bdf14d6176680cb3de833 (patch) | |
| tree | bf5fd721b3c287b9a2a62d0664e2c107fee6eafc /usrp2/extramfifo/nobl_fifo.v | |
| parent | 8507271de44aadc564354a77c8b9259e24f0d246 (diff) | |
| download | uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.tar.gz uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.tar.bz2 uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.zip | |
Added external RAM FIFO to u2plus.
Added code branch to ext_fifo.v using generate that instantiates
different input and out fifo's and touched nobl_fifo code so that it
works at 18 and 36bit widths.
Added 2nd DCM to top level to generate off chip RAMCLK.
Added explicit I/O instances to top level for tristate drivers and
changed signals to core as needed.
Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
Diffstat (limited to 'usrp2/extramfifo/nobl_fifo.v')
| -rw-r--r-- | usrp2/extramfifo/nobl_fifo.v | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 4c009d980..0b63768fc 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -70,26 +70,27 @@ module nobl_fifo // Simple NoBL SRAM interface, 4 cycle read latency. // Read/Write arbitration via temprary application of empty/full flags. // - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); + nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) + nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); |