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| author | Matt Ettus <matt@ettus.com> | 2010-07-14 16:46:01 -0700 |
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| committer | Matt Ettus <matt@ettus.com> | 2010-07-14 16:46:01 -0700 |
| commit | bd455159a0b60eb2c496322d0f80c3ca77d838f6 (patch) | |
| tree | 43cc769286ef489fac8d432023b5fe380014f20e /usrp2/extramfifo/fifo_extram_tb.build | |
| parent | 458e0da01b8c169204ecdce8972f7e36aa59fdf2 (diff) | |
| download | uhd-bd455159a0b60eb2c496322d0f80c3ca77d838f6.tar.gz uhd-bd455159a0b60eb2c496322d0f80c3ca77d838f6.tar.bz2 uhd-bd455159a0b60eb2c496322d0f80c3ca77d838f6.zip | |
moved forward from the old branch
Diffstat (limited to 'usrp2/extramfifo/fifo_extram_tb.build')
| -rw-r--r-- | usrp2/extramfifo/fifo_extram_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build new file mode 100644 index 000000000..e87217e5c --- /dev/null +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |