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| author | Matt Ettus <matt@ettus.com> | 2010-07-14 16:46:01 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 11:36:09 -0800 |
| commit | f9db9f4eed98a7538d73b5463e762441198526c1 (patch) | |
| tree | b4b92b71e2389e1fe575769510c361bd097d90e8 /usrp2/extramfifo/fifo_extram36_tb.build | |
| parent | f64f1b5c86c605b7c769bbedd565e356d08e925d (diff) | |
| download | uhd-f9db9f4eed98a7538d73b5463e762441198526c1.tar.gz uhd-f9db9f4eed98a7538d73b5463e762441198526c1.tar.bz2 uhd-f9db9f4eed98a7538d73b5463e762441198526c1.zip | |
moved forward from the old branch
Diffstat (limited to 'usrp2/extramfifo/fifo_extram36_tb.build')
| -rw-r--r-- | usrp2/extramfifo/fifo_extram36_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100644 index 000000000..699591889 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v |