Checkpoint checkin.

Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.

1 files changed, 9 insertions, 0 deletions

diff --git a/usrp2/extramfifo/ext_fifo_tb.prj b/usrp2/extramfifo/ext_fifo_tb.prj
new file mode 100644
index 000000000..a11a15b2f
--- /dev/null
+++ b/usrp2/extramfifo/ext_fifo_tb.prj
@@ -0,0 +1,9 @@
+verilog work "./ext_fifo_tb.v"
+verilog work "./ext_fifo.v"
+verilog work "./nobl_fifo.v"
+verilog work "./nobl_if.v"
+verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v"
+verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v"
+verilog work "../models/CY7C1356C/cy1356.v"
+verilog work "../models/idt71v65603s150.v"
+verilog work "$XILINX/verilog/src/glbl.v"