Added external RAM FIFO to u2plus.

Added code branch to ext_fifo.v using generate that instantiates
different input and out fifo's and touched nobl_fifo code so that it
works at 18 and 36bit widths.
Added 2nd DCM to top level to generate off chip RAMCLK.
Added explicit I/O instances to top level for tristate drivers and
changed signals to core as needed.
Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3

1 files changed, 78 insertions, 37 deletions

diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index 2af59a75d..2a8d57448 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -18,7 +18,7 @@
  //`define NO_EXT_FIFO
 
 module ext_fifo
-   #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+  #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
     (
      input int_clk,
      input ext_clk,
@@ -44,34 +44,29 @@ module ext_fifo
 
    wire [EXT_WIDTH-1:0] write_data;
    wire [EXT_WIDTH-1:0] read_data;
-   wire 	    full1, empty1;
-   wire 	    almost_full2, full2, empty2;
+   wire 		full1, empty1;
+   wire 		almost_full2, full2, empty2;
    wire [INT_WIDTH-1:0] data_to_fifo;
    wire [INT_WIDTH-1:0] data_from_fifo;
    wire [FIFO_DEPTH-1:0] capacity;
-		
+   wire 		 space_avail;
+   wire 		 data_avail;
+		 
+   // These next 2 lines here purely because ICARUS is crap at handling generate statements.
+   // Empirically this has been determined to make simulations work.
+   wire 		 read_input_fifo = space_avail & ~empty1;
+   wire 		 write_output_fifo = data_avail;
    
-   // FIFO buffers data from UDP engine into external FIFO clock domain.
-   fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
-								 .rst(rst),
-								 .wr_clk(int_clk),
-								 .rd_clk(ext_clk),
-								 .din(datain), // Bus [35 : 0]						
-								 .wr_en(src_rdy_i),						
-								 .rd_en(space_avail&~empty1),						
-								 .dout(write_data), // Bus [17 : 0] 
-								 .full(full1),			
-							         .empty(empty1));
-
-    assign 	    dst_rdy_o = ~full1;
+   assign 		 src_rdy_o = ~empty2;
+   assign 		 dst_rdy_o = ~full1;
 
 `ifdef NO_EXT_FIFO
-   assign 	    space_avail = ~full2;
-   assign 	    data_avail = ~empty1;
-   assign 	    read_data = write_data;
+   assign 		 space_avail = ~full2;
+   assign 		 data_avail = ~empty1;
+   assign 		 read_data = write_data;
 `else
    
-   // External FIFO running at ext clock rate  and 18 bit width.
+   // External FIFO running at ext clock rate  and 18 or 36 bit width.
    nobl_fifo  #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH))
      nobl_fifo_i1
        (   
@@ -95,22 +90,67 @@ module ext_fifo
 	   .capacity(capacity)
 	   );
 `endif // !`ifdef NO_EXT_FIFO
+
    
- 
-   // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
-   fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
-								 .rst(rst),
-								 .wr_clk(ext_clk),
-								 .rd_clk(int_clk),
-								 .din(read_data), // Bus [17 : 0]
-								 .wr_en(data_avail),
-								 .rd_en(dst_rdy_i),
-								 .dout(dataout), // Bus [35 : 0]
-								 .full(full2),
-								 .prog_full(almost_full2),
-								 .empty(empty2));
-   assign  src_rdy_o = ~empty2;
+   generate
+      if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1
+	 // FIFO buffers data from UDP engine into external FIFO clock domain.
+	 fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
+								       .rst(rst),
+								       .wr_clk(int_clk),
+								       .rd_clk(ext_clk),
+								       .din(datain), // Bus [35 : 0] 
+								       .wr_en(src_rdy_i), 
+								       .rd_en(read_input_fifo),    		
+								       .dout(write_data), // Bus [17 : 0]
+								       .full(full1),			
+							               .empty(empty1));
 
+	 
+	 // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+	 fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
+								       .rst(rst),
+								       .wr_clk(ext_clk),
+								       .rd_clk(int_clk),
+								       .din(read_data), // Bus [17 : 0]
+								       .wr_en(write_output_fifo),
+								       .rd_en(dst_rdy_i),
+								       .dout(dataout), // Bus [35 : 0]
+								       .full(full2),
+								       .prog_full(almost_full2),
+								       .empty(empty2));
+      end // block: fifo_g1
+      else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1
+	 // FIFO buffers data from UDP engine into external FIFO clock domain.
+	 fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 (
+						       .rst(rst),
+						       .wr_clk(int_clk),
+						       .rd_clk(ext_clk),
+						       .din(datain), // Bus [35 : 0] 
+						       .wr_en(src_rdy_i),
+						       .rd_en(read_input_fifo),
+						       .dout(write_data), // Bus [35 : 0] 
+						       .full(full1),
+						       .empty(empty1));
+	 
+	 // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+	 fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 (
+						       .rst(rst),
+						       .wr_clk(ext_clk),
+						       .rd_clk(int_clk),
+						       .din(read_data), // Bus [35 : 0] 
+						       .wr_en(write_output_fifo),
+						       .rd_en(dst_rdy_i),
+						       .dout(dataout), // Bus [35 : 0] 
+						       .full(full2),
+						       .empty(empty2),
+						       .prog_full(almost_full2));
+
+      end    
+   endgenerate
+   
+
+   
    always @ (posedge int_clk)
      debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
    
@@ -118,6 +158,7 @@ module ext_fifo
      debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
 
    always@ (posedge ext_clk)
-//     debug2[31:0] <= {write_data[15:0],read_data[15:0]};
-       debug2[31:0] <= 0;
+     //     debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+     debug2[31:0] <= 0;
+   
 endmodule // ext_fifo