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| author | Ian Buckley <ian.buckley@gmail.com> | 2010-11-11 10:06:36 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:15:40 -0800 |
| commit | 51d68f095f2341e93232683bd6e3660285478196 (patch) | |
| tree | d8d31e3a210fba304351c71ca1b9f281f797c9a5 /usrp2/extramfifo/ext_fifo.v | |
| parent | 4e5f4e137e70728116536ac19f1bf946fa890b7d (diff) | |
| download | uhd-51d68f095f2341e93232683bd6e3660285478196.tar.gz uhd-51d68f095f2341e93232683bd6e3660285478196.tar.bz2 uhd-51d68f095f2341e93232683bd6e3660285478196.zip | |
1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable full watermark
2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
Diffstat (limited to 'usrp2/extramfifo/ext_fifo.v')
| -rw-r--r-- | usrp2/extramfifo/ext_fifo.v | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 44229f846..daf7140bc 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -132,17 +132,17 @@ module ext_fifo .empty(empty1)); // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [35 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .empty(empty2), - .prog_full(almost_full2)); + fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); end endgenerate |