Corrected extfifo code so that all registers that are on SRAM signals are packed into IOBs

Explcit drives and skews added to GPIO pins

Corrected minor error in FIFO logic that showed data avail internally incorrectly

1 files changed, 7 insertions, 3 deletions

diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index b17fde10b..2af59a75d 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -38,7 +38,8 @@ module ext_fifo
      output [INT_WIDTH-1:0] dataout,
      output src_rdy_o,               // not EMPTY
      input dst_rdy_i,                 // READ
-     output reg [31:0] debug
+     output reg [31:0] debug,
+     output reg [31:0] debug2
      );
 
    wire [EXT_WIDTH-1:0] write_data;
@@ -111,9 +112,12 @@ module ext_fifo
    assign  src_rdy_o = ~empty2;
 
    always @ (posedge int_clk)
-     debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i };
+     debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
    
    always @ (posedge ext_clk)
-     debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] };
+     debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
 
+   always@ (posedge ext_clk)
+//     debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+       debug2[31:0] <= 0;
 endmodule // ext_fifo