dsp rework: rehash of the custom module stuff and readme

5 files changed, 29 insertions, 222 deletions

diff --git a/usrp2/custom/Makefile.srcs b/usrp2/custom/Makefile.srcs
deleted file mode 100644
index 8a4f70fca..000000000
--- a/usrp2/custom/Makefile.srcs
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2012 Ettus Research LLC
-#
-
-##################################################
-# FIFO Sources
-##################################################
-CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \
-custom_dsp_rx.v \
-custom_dsp_tx.v \
-custom_engine_rx.v \
-custom_engine_tx.v \
-))
diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
index 73294566e..b90cd54e9 100644
--- a/usrp2/custom/custom_dsp_rx.v
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-//CUSTOMIZE ME!
+//COPY ME, CUSTOMIZE ME...
 
 //The following module effects the IO of the DDC chain.
 //By default, this entire module is a simple pass-through.
@@ -31,9 +31,6 @@
 
 module custom_dsp_rx
 #(
-    //the dsp unit number: 0, 1, 2...
-    parameter DSPNO = 0,
-
     //frontend bus width
     parameter WIDTH = 24
 )
@@ -41,11 +38,8 @@ module custom_dsp_rx
     //control signals
     input clock, input reset, input enable,
 
-    //main settings bus for built-in modules
-    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
-
     //user settings bus, controlled through user setting regs API
-    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
     //full rate inputs directly from the RX frontend
     input [WIDTH-1:0] frontend_i,
@@ -61,49 +55,12 @@ module custom_dsp_rx
 
     //strobbed baseband samples {I16,Q16} from this module
     output [31:0] bb_sample,
-    output bb_strobe, //high on valid sample
-
-    //debug output (optional)
-    output [31:0] debug
+    output bb_strobe //high on valid sample
 );
 
-    generate
-        if (DSPNO==0) begin
-            `ifndef RX_DSP0_MODULE
-            assign ddc_in_i = frontend_i;
-            assign ddc_in_q = frontend_q;
-            assign bb_sample = ddc_out_sample;
-            assign bb_strobe = ddc_out_strobe;
-            `else
-            RX_DSP0_CUSTOM_MODULE_NAME rx_dsp0_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
-                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-        else begin
-            `ifndef RX_DSP1_MODULE
-            assign ddc_in_i = frontend_i;
-            assign ddc_in_q = frontend_q;
-            assign bb_sample = ddc_out_sample;
-            assign bb_strobe = ddc_out_strobe;
-            `else
-            RX_DSP1_CUSTOM_MODULE_NAME rx_dsp1_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
-                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-    endgenerate
+    assign ddc_in_i = frontend_i;
+    assign ddc_in_q = frontend_q;
+    assign bb_sample = ddc_out_sample;
+    assign bb_strobe = ddc_out_strobe;
 
 endmodule //custom_dsp_rx
diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v
index cb0d7522b..4b1388b02 100644
--- a/usrp2/custom/custom_dsp_tx.v
+++ b/usrp2/custom/custom_dsp_tx.v
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-//CUSTOMIZE ME!
+//COPY ME, CUSTOMIZE ME...
 
 //The following module effects the IO of the DUC chain.
 //By default, this entire module is a simple pass-through.
@@ -31,9 +31,6 @@
 
 module custom_dsp_tx
 #(
-    //the dsp unit number: 0, 1, 2...
-    parameter DSPNO = 0,
-
     //frontend bus width
     parameter WIDTH = 24
 )
@@ -41,11 +38,8 @@ module custom_dsp_tx
     //control signals
     input clock, input reset, input enable,
 
-    //main settings bus for built-in modules
-    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
-
     //user settings bus, controlled through user setting regs API
-    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
     //full rate outputs directly to the TX frontend
     output [WIDTH-1:0] frontend_i,
@@ -61,49 +55,12 @@ module custom_dsp_tx
 
     //strobbed baseband samples {I16,Q16} to this module
     input [31:0] bb_sample,
-    output bb_strobe, //this is a backpressure signal
-
-    //debug output (optional)
-    output [31:0] debug
+    output bb_strobe //this is a backpressure signal
 );
 
-    generate
-        if (DSPNO==0) begin
-            `ifndef TX_DSP0_MODULE
-            assign frontend_i = duc_out_i;
-            assign frontend_q = duc_out_q;
-            assign duc_in_sample = bb_sample;
-            assign bb_strobe = duc_in_strobe;
-            `else
-            TX_DSP0_CUSTOM_MODULE_NAME tx_dsp0_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
-                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-        else begin
-            `ifndef TX_DSP1_MODULE
-            assign frontend_i = duc_out_i;
-            assign frontend_q = duc_out_q;
-            assign duc_in_sample = bb_sample;
-            assign bb_strobe = duc_in_strobe;
-            `else
-            TX_DSP1_CUSTOM_MODULE_NAME tx_dsp1_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
-                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-    endgenerate
+    assign frontend_i = duc_out_i;
+    assign frontend_q = duc_out_q;
+    assign duc_in_sample = bb_sample;
+    assign bb_strobe = duc_in_strobe;
 
 endmodule //custom_dsp_tx
diff --git a/usrp2/custom/custom_engine_rx.v b/usrp2/custom/custom_engine_rx.v
index 48276665f..dfeaad2cd 100644
--- a/usrp2/custom/custom_engine_rx.v
+++ b/usrp2/custom/custom_engine_rx.v
@@ -15,35 +15,26 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-//CUSTOMIZE ME!
+//COPY ME, CUSTOMIZE ME...
 
 //The following module is used to re-write receive packets to the host.
 //This module provides a packet-based ram interface for manipulating packets.
 //The user writes a custom engine (state machine) to read the input packet,
-//and to produce a new output packet. For users customizing the DSP operation,
-//your customizations may be better suited for the custom_dsp_rx module.
-//By default, this module uses the built-in 16 to 8 bit converter engine.
+//and to produce a new output packet.
+
+//By default, this entire module is a simple pass-through.
 
 module custom_engine_rx
 #(
-    //the dsp unit number: 0, 1, 2...
-    parameter DSPNO = 0,
-
     //buffer size for ram interface engine
-    parameter BUF_SIZE = 10,
-
-    //base address for built-in settings registers used in this module
-    parameter MAIN_SETTINGS_BASE = 0
+    parameter BUF_SIZE = 10
 )
 (
     //control signals
     input clock, input reset, input clear,
 
-    //main settings bus for built-in modules
-    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
-
     //user settings bus, controlled through user setting regs API
-    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
     //ram interface for engine
     output access_we,
@@ -54,47 +45,9 @@ module custom_engine_rx
     output [BUF_SIZE-1:0] access_adr,
     input [BUF_SIZE-1:0] access_len,
     output [35:0] access_dat_o,
-    input [35:0] access_dat_i,
-
-    //debug output (optional)
-    output [31:0] debug
+    input [35:0] access_dat_i
 );
 
-    generate
-        if (DSPNO==0) begin
-            `ifndef RX_ENG0_MODULE
-            dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
-             (.clk(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `else
-            RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom
-             (.clock(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `endif
-        end
-        else begin
-            `ifndef RX_ENG1_MODULE
-            dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
-             (.clk(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `else
-            RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom
-             (.clock(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `endif
-        end
-    endgenerate
+    assign access_done = access_ok;
 
 endmodule //custom_engine_rx
diff --git a/usrp2/custom/custom_engine_tx.v b/usrp2/custom/custom_engine_tx.v
index 6227b0f45..9be728484 100644
--- a/usrp2/custom/custom_engine_tx.v
+++ b/usrp2/custom/custom_engine_tx.v
@@ -15,26 +15,20 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-//CUSTOMIZE ME!
+//COPY ME, CUSTOMIZE ME...
 
 //The following module is used to re-write transmit packets from the host.
 //This module provides a packet-based ram interface for manipulating packets.
 //The user writes a custom engine (state machine) to read the input packet,
-//and to produce a new output packet. For users customizing the DSP operation,
-//your customizations may be better suited for the custom_dsp_tx module.
-//By default, this module uses the built-in 8 to 16 bit converter engine.
+//and to produce a new output packet.
+
+//By default, this entire module is a simple pass-through.
 
 module custom_engine_tx
 #(
-    //the dsp unit number: 0, 1, 2...
-    parameter DSPNO = 0,
-
     //buffer size for ram interface engine
     parameter BUF_SIZE = 10,
 
-    //base address for built-in settings registers used in this module
-    parameter MAIN_SETTINGS_BASE = 0,
-
     //the number of 32bit lines between start of buffer and vita header
     //the metadata before the header should be preserved by the engine
     parameter HEADER_OFFSET = 0
@@ -43,11 +37,8 @@ module custom_engine_tx
     //control signals
     input clock, input reset, input clear,
 
-    //main settings bus for built-in modules
-    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
-
     //user settings bus, controlled through user setting regs API
-    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
     //ram interface for engine
     output access_we,
@@ -58,47 +49,9 @@ module custom_engine_tx
     output [BUF_SIZE-1:0] access_adr,
     input [BUF_SIZE-1:0] access_len,
     output [35:0] access_dat_o,
-    input [35:0] access_dat_i,
-
-    //debug output (optional)
-    output [31:0] debug
+    input [35:0] access_dat_i
 );
 
-    generate
-        if (DSPNO==0) begin
-            `ifndef TX_ENG0_MODULE
-            dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
-             (.clk(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `else
-            TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng0_custom
-             (.clock(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `endif
-        end
-        else begin
-            `ifndef TX_ENG1_MODULE
-            dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
-             (.clk(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `else
-            TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng1_custom
-             (.clock(clock),.reset(reset),.clear(clear),
-              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
-              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
-              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
-              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
-            `endif
-        end
-    endgenerate
+    assign access_done = access_ok;
 
 endmodule //custom_engine_tx