dsp rework: pass vita clears into dsp modules, unified fifo clears

2 files changed, 8 insertions, 2 deletions

diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
index b90cd54e9..2ceda7481 100644
--- a/usrp2/custom/custom_dsp_rx.v
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -36,7 +36,10 @@ module custom_dsp_rx
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v
index 4b1388b02..5206a63a6 100644
--- a/usrp2/custom/custom_dsp_tx.v
+++ b/usrp2/custom/custom_dsp_tx.v
@@ -36,7 +36,10 @@ module custom_dsp_tx
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,