dsp rework: custom engine module for rx/tx vita chain

5 files changed, 234 insertions, 88 deletions

diff --git a/usrp2/custom/Makefile.srcs b/usrp2/custom/Makefile.srcs
index 22cf063c9..8a4f70fca 100644
--- a/usrp2/custom/Makefile.srcs
+++ b/usrp2/custom/Makefile.srcs
@@ -8,4 +8,6 @@
 CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \
 custom_dsp_rx.v \
 custom_dsp_tx.v \
+custom_engine_rx.v \
+custom_engine_tx.v \
 ))
diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
index 64f966c31..73294566e 100644
--- a/usrp2/custom/custom_dsp_rx.v
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -31,23 +31,29 @@
 
 module custom_dsp_rx
 #(
+    //the dsp unit number: 0, 1, 2...
     parameter DSPNO = 0,
-    parameter ADCW = 24
+
+    //frontend bus width
+    parameter WIDTH = 24
 )
 (
     //control signals
     input clock, input reset, input enable,
 
-    //settings bus
-    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    //main settings bus for built-in modules
+    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
     //full rate inputs directly from the RX frontend
-    input [ADCW-1:0] frontend_i,
-    input [ADCW-1:0] frontend_q,
+    input [WIDTH-1:0] frontend_i,
+    input [WIDTH-1:0] frontend_q,
 
     //full rate outputs directly to the DDC chain
-    output [ADCW-1:0] ddc_in_i,
-    output [ADCW-1:0] ddc_in_q,
+    output [WIDTH-1:0] ddc_in_i,
+    output [WIDTH-1:0] ddc_in_q,
 
     //strobed samples {I16,Q16} from the RX DDC chain
     input [31:0] ddc_out_sample,
@@ -80,7 +86,7 @@ module custom_dsp_rx
             );
             `endif
         end
-        if (DSPNO==1) begin
+        else begin
             `ifndef RX_DSP1_MODULE
             assign ddc_in_i = frontend_i;
             assign ddc_in_q = frontend_q;
@@ -98,42 +104,6 @@ module custom_dsp_rx
             );
             `endif
         end
-        if (DSPNO==2) begin
-            `ifndef RX_DSP2_MODULE
-            assign ddc_in_i = frontend_i;
-            assign ddc_in_q = frontend_q;
-            assign bb_sample = ddc_out_sample;
-            assign bb_strobe = ddc_out_strobe;
-            `else
-            RX_DSP2_CUSTOM_MODULE_NAME rx_dsp2_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
-                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-        else begin
-            `ifndef RX_DSP3_MODULE
-            assign ddc_in_i = frontend_i;
-            assign ddc_in_q = frontend_q;
-            assign bb_sample = ddc_out_sample;
-            assign bb_strobe = ddc_out_strobe;
-            `else
-            RX_DSP3_CUSTOM_MODULE_NAME rx_dsp3_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
-                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
     endgenerate
 
 endmodule //custom_dsp_rx
diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v
index 102805139..cb0d7522b 100644
--- a/usrp2/custom/custom_dsp_tx.v
+++ b/usrp2/custom/custom_dsp_tx.v
@@ -31,23 +31,29 @@
 
 module custom_dsp_tx
 #(
+    //the dsp unit number: 0, 1, 2...
     parameter DSPNO = 0,
-    parameter ADCW = 24
+
+    //frontend bus width
+    parameter WIDTH = 24
 )
 (
     //control signals
     input clock, input reset, input enable,
 
-    //settings bus
-    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    //main settings bus for built-in modules
+    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
     //full rate outputs directly to the TX frontend
-    output [ADCW-1:0] frontend_i,
-    output [ADCW-1:0] frontend_q,
+    output [WIDTH-1:0] frontend_i,
+    output [WIDTH-1:0] frontend_q,
 
     //full rate outputs directly from the DUC chain
-    input [ADCW-1:0] duc_out_i,
-    input [ADCW-1:0] duc_out_q,
+    input [WIDTH-1:0] duc_out_i,
+    input [WIDTH-1:0] duc_out_q,
 
     //strobed samples {I16,Q16} to the TX DUC chain
     output [31:0] duc_in_sample,
@@ -80,7 +86,7 @@ module custom_dsp_tx
             );
             `endif
         end
-        if (DSPNO==1) begin
+        else begin
             `ifndef TX_DSP1_MODULE
             assign frontend_i = duc_out_i;
             assign frontend_q = duc_out_q;
@@ -98,42 +104,6 @@ module custom_dsp_tx
             );
             `endif
         end
-        if (DSPNO==2) begin
-            `ifndef TX_DSP2_MODULE
-            assign frontend_i = duc_out_i;
-            assign frontend_q = duc_out_q;
-            assign duc_in_sample = bb_sample;
-            assign bb_strobe = duc_in_strobe;
-            `else
-            TX_DSP2_CUSTOM_MODULE_NAME tx_dsp2_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
-                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
-        else begin
-            `ifndef TX_DSP3_MODULE
-            assign frontend_i = duc_out_i;
-            assign frontend_q = duc_out_q;
-            assign duc_in_sample = bb_sample;
-            assign bb_strobe = duc_in_strobe;
-            `else
-            TX_DSP3_CUSTOM_MODULE_NAME tx_dsp3_custom
-            (
-                .clock(clock), .reset(reset), .enable(enable),
-                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-                .frontend_i(frontend_i), .frontend_q(frontend_q),
-                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
-                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
-                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
-            );
-            `endif
-        end
     endgenerate
 
 endmodule //custom_dsp_tx
diff --git a/usrp2/custom/custom_engine_rx.v b/usrp2/custom/custom_engine_rx.v
new file mode 100644
index 000000000..48276665f
--- /dev/null
+++ b/usrp2/custom/custom_engine_rx.v
@@ -0,0 +1,100 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//CUSTOMIZE ME!
+
+//The following module is used to re-write receive packets to the host.
+//This module provides a packet-based ram interface for manipulating packets.
+//The user writes a custom engine (state machine) to read the input packet,
+//and to produce a new output packet. For users customizing the DSP operation,
+//your customizations may be better suited for the custom_dsp_rx module.
+//By default, this module uses the built-in 16 to 8 bit converter engine.
+
+module custom_engine_rx
+#(
+    //the dsp unit number: 0, 1, 2...
+    parameter DSPNO = 0,
+
+    //buffer size for ram interface engine
+    parameter BUF_SIZE = 10,
+
+    //base address for built-in settings registers used in this module
+    parameter MAIN_SETTINGS_BASE = 0
+)
+(
+    //control signals
+    input clock, input reset, input clear,
+
+    //main settings bus for built-in modules
+    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+
+    //ram interface for engine
+    output access_we,
+    output access_stb,
+    input access_ok,
+    output access_done,
+    output access_skip_read,
+    output [BUF_SIZE-1:0] access_adr,
+    input [BUF_SIZE-1:0] access_len,
+    output [35:0] access_dat_o,
+    input [35:0] access_dat_i,
+
+    //debug output (optional)
+    output [31:0] debug
+);
+
+    generate
+        if (DSPNO==0) begin
+            `ifndef RX_ENG0_MODULE
+            dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
+             (.clk(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `else
+            RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom
+             (.clock(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `endif
+        end
+        else begin
+            `ifndef RX_ENG1_MODULE
+            dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
+             (.clk(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `else
+            RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom
+             (.clock(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `endif
+        end
+    endgenerate
+
+endmodule //custom_engine_rx
diff --git a/usrp2/custom/custom_engine_tx.v b/usrp2/custom/custom_engine_tx.v
new file mode 100644
index 000000000..6227b0f45
--- /dev/null
+++ b/usrp2/custom/custom_engine_tx.v
@@ -0,0 +1,104 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//CUSTOMIZE ME!
+
+//The following module is used to re-write transmit packets from the host.
+//This module provides a packet-based ram interface for manipulating packets.
+//The user writes a custom engine (state machine) to read the input packet,
+//and to produce a new output packet. For users customizing the DSP operation,
+//your customizations may be better suited for the custom_dsp_tx module.
+//By default, this module uses the built-in 8 to 16 bit converter engine.
+
+module custom_engine_tx
+#(
+    //the dsp unit number: 0, 1, 2...
+    parameter DSPNO = 0,
+
+    //buffer size for ram interface engine
+    parameter BUF_SIZE = 10,
+
+    //base address for built-in settings registers used in this module
+    parameter MAIN_SETTINGS_BASE = 0,
+
+    //the number of 32bit lines between start of buffer and vita header
+    //the metadata before the header should be preserved by the engine
+    parameter HEADER_OFFSET = 0
+)
+(
+    //control signals
+    input clock, input reset, input clear,
+
+    //main settings bus for built-in modules
+    input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
+
+    //ram interface for engine
+    output access_we,
+    output access_stb,
+    input access_ok,
+    output access_done,
+    output access_skip_read,
+    output [BUF_SIZE-1:0] access_adr,
+    input [BUF_SIZE-1:0] access_len,
+    output [35:0] access_dat_o,
+    input [35:0] access_dat_i,
+
+    //debug output (optional)
+    output [31:0] debug
+);
+
+    generate
+        if (DSPNO==0) begin
+            `ifndef TX_ENG0_MODULE
+            dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
+             (.clk(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `else
+            TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng0_custom
+             (.clock(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `endif
+        end
+        else begin
+            `ifndef TX_ENG1_MODULE
+            dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
+             (.clk(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `else
+            TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng1_custom
+             (.clock(clock),.reset(reset),.clear(clear),
+              .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+              .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+              .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+              .access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
+            `endif
+        end
+    endgenerate
+
+endmodule //custom_engine_tx