aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/custom/custom_dsp_rx.v
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2012-02-01 18:02:10 -0800
committerJosh Blum <josh@joshknows.com>2012-02-01 18:02:10 -0800
commit7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f (patch)
tree31bf389f0a241d4309bb042450dad4be81f39b3c /usrp2/custom/custom_dsp_rx.v
parent6bbcb202183c5a0ab5351a0c052981408e4719cb (diff)
downloaduhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.gz
uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.bz2
uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.zip
dsp rework: custom engine module for rx/tx vita chain
Diffstat (limited to 'usrp2/custom/custom_dsp_rx.v')
-rw-r--r--usrp2/custom/custom_dsp_rx.v58
1 files changed, 14 insertions, 44 deletions
diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
index 64f966c31..73294566e 100644
--- a/usrp2/custom/custom_dsp_rx.v
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -31,23 +31,29 @@
module custom_dsp_rx
#(
+ //the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
- parameter ADCW = 24
+
+ //frontend bus width
+ parameter WIDTH = 24
)
(
//control signals
input clock, input reset, input enable,
- //settings bus
- input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ //main settings bus for built-in modules
+ input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
+
+ //user settings bus, controlled through user setting regs API
+ input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
//full rate inputs directly from the RX frontend
- input [ADCW-1:0] frontend_i,
- input [ADCW-1:0] frontend_q,
+ input [WIDTH-1:0] frontend_i,
+ input [WIDTH-1:0] frontend_q,
//full rate outputs directly to the DDC chain
- output [ADCW-1:0] ddc_in_i,
- output [ADCW-1:0] ddc_in_q,
+ output [WIDTH-1:0] ddc_in_i,
+ output [WIDTH-1:0] ddc_in_q,
//strobed samples {I16,Q16} from the RX DDC chain
input [31:0] ddc_out_sample,
@@ -80,7 +86,7 @@ module custom_dsp_rx
);
`endif
end
- if (DSPNO==1) begin
+ else begin
`ifndef RX_DSP1_MODULE
assign ddc_in_i = frontend_i;
assign ddc_in_q = frontend_q;
@@ -98,42 +104,6 @@ module custom_dsp_rx
);
`endif
end
- if (DSPNO==2) begin
- `ifndef RX_DSP2_MODULE
- assign ddc_in_i = frontend_i;
- assign ddc_in_q = frontend_q;
- assign bb_sample = ddc_out_sample;
- assign bb_strobe = ddc_out_strobe;
- `else
- RX_DSP2_CUSTOM_MODULE_NAME rx_dsp2_custom
- (
- .clock(clock), .reset(reset), .enable(enable),
- .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
- .frontend_i(frontend_i), .frontend_q(frontend_q),
- .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
- .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
- .bb_sample(bb_sample), .bb_strobe(bb_strobe)
- );
- `endif
- end
- else begin
- `ifndef RX_DSP3_MODULE
- assign ddc_in_i = frontend_i;
- assign ddc_in_q = frontend_q;
- assign bb_sample = ddc_out_sample;
- assign bb_strobe = ddc_out_strobe;
- `else
- RX_DSP3_CUSTOM_MODULE_NAME rx_dsp3_custom
- (
- .clock(clock), .reset(reset), .enable(enable),
- .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
- .frontend_i(frontend_i), .frontend_q(frontend_q),
- .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
- .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
- .bb_sample(bb_sample), .bb_strobe(bb_strobe)
- );
- `endif
- end
endgenerate
endmodule //custom_dsp_rx