Checkpoint checkin.

Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.

4 files changed, 494 insertions, 0 deletions

diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
new file mode 100644
index 000000000..1d7a5ca2a
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
@@ -0,0 +1,165 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating
+// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_18to36(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full);
+
+
+input [17 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [35 : 0] dout;
+output empty;
+output full;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_4 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(10),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(18),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(0),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(0),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(0),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("1kx18"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(9),
+		.C_RD_DEPTH(512),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(9),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(0),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(10),
+		.C_WR_DEPTH(1024),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(10),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.RD_DATA_COUNT(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.WR_DATA_COUNT(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
new file mode 100644
index 000000000..df97fd0e0
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Jul 29 23:02:41 2010
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_512x36_2clk_18to36
+CSET data_count=false
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=1023
+CSET full_threshold_negate_value=1022
+CSET input_data_width=18
+CSET input_depth=1024
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: 117ae77f
+
diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
new file mode 100644
index 000000000..f7f6e7e9f
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
@@ -0,0 +1,165 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating
+// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_36to18(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full);
+
+
+input [35 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [17 : 0] dout;
+output empty;
+output full;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_4 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(9),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(18),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(0),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(0),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(0),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(509),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(508),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(10),
+		.C_RD_DEPTH(1024),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(10),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(0),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(9),
+		.C_WR_DEPTH(512),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(9),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.RD_DATA_COUNT(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.WR_DATA_COUNT(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
new file mode 100644
index 000000000..a1c75dc39
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Jul 29 18:10:59 2010
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_512x36_2clk_36to18
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=509
+CSET full_threshold_negate_value=508
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=18
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: 392ad537
+