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| author | Matt Ettus <matt@ettus.com> | 2010-05-11 15:49:48 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-11 15:49:48 -0700 | 
| commit | 9899b81f920b8dab0220e2e4b086bae0f24f6970 (patch) | |
| tree | 45ccbd04a3d2c347b36197e8d110a0ff7c810a40 /usrp2/control_lib | |
| parent | 93185ca7719e8949e90b594676be6c3d2f709fb9 (diff) | |
| download | uhd-9899b81f920b8dab0220e2e4b086bae0f24f6970.tar.gz uhd-9899b81f920b8dab0220e2e4b086bae0f24f6970.tar.bz2 uhd-9899b81f920b8dab0220e2e4b086bae0f24f6970.zip | |
cleaned up the logic, this is copied over from quad radio
Diffstat (limited to 'usrp2/control_lib')
| -rw-r--r-- | usrp2/control_lib/settings_bus.v | 18 | 
1 files changed, 5 insertions, 13 deletions
| diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v index d01a30ab4..aec179516 100644 --- a/usrp2/control_lib/settings_bus.v +++ b/usrp2/control_lib/settings_bus.v @@ -10,8 +10,7 @@ module settings_bus       input wb_stb_i,       input wb_we_i,       output reg wb_ack_o, -     input sys_clk, -     output strobe, +     output reg strobe,       output reg [7:0] addr,       output reg [31:0] data); @@ -20,18 +19,18 @@ module settings_bus     always @(posedge wb_clk)       if(wb_rst)         begin -	  stb_int <= 1'b0; +	  strobe <= 1'b0;  	  addr <= 8'd0;  	  data <= 32'd0;         end -     else if(wb_we_i & wb_stb_i) +     else if(wb_we_i & wb_stb_i & ~wb_ack_o)         begin -	  stb_int <= 1'b1; +	  strobe <= 1'b1;  	  addr <= wb_adr_i[9:2];  	  data <= wb_dat_i;         end       else -       stb_int <= 1'b0; +       strobe <= 1'b0;     always @(posedge wb_clk)       if(wb_rst) @@ -39,11 +38,4 @@ module settings_bus       else         wb_ack_o <= wb_stb_i & ~wb_ack_o; -   always @(posedge wb_clk) -     stb_int_d1 <= stb_int; - -   //assign strobe = stb_int & ~stb_int_d1; -   assign strobe = stb_int & wb_ack_o; -            endmodule // settings_bus - | 
