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| author | Matt Ettus <matt@ettus.com> | 2011-08-24 16:07:04 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-26 13:24:37 -0700 |
| commit | 7cd90f705a07b130dd8d8ffd859a8ebbd3abfa58 (patch) | |
| tree | f538b7beb97348a4b897e4ed644e36ddc67974a3 /usrp2/control_lib | |
| parent | 311fcf1abad690a6eaee24069bd4c1679623deee (diff) | |
| download | uhd-7cd90f705a07b130dd8d8ffd859a8ebbd3abfa58.tar.gz uhd-7cd90f705a07b130dd8d8ffd859a8ebbd3abfa58.tar.bz2 uhd-7cd90f705a07b130dd8d8ffd859a8ebbd3abfa58.zip | |
fix typo
Diffstat (limited to 'usrp2/control_lib')
| -rw-r--r-- | usrp2/control_lib/bootram.v | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 77af7f3a3..7821fbc4c 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -112,8 +112,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -123,7 +123,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB1), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -142,8 +142,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -153,7 +153,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB2), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -172,8 +172,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -183,7 +183,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB3), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -202,8 +202,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -213,7 +213,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB4), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -232,8 +232,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -243,7 +243,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB5), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -262,8 +262,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -273,7 +273,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB6), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -292,8 +292,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'dffffffff), // Port A 32-bit Data Input - .DIPA(4'df), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -303,7 +303,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'df), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB7), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input |