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authorMatt Ettus <matt@ettus.com>2010-02-23 19:54:54 -0800
committerMatt Ettus <matt@ettus.com>2010-02-23 19:54:54 -0800
commit702c87c3bae259f038d2c10fe32903f391e95de1 (patch)
treed95fea5fd16641701ab352c962119efa7127e292 /usrp2/control_lib
parent89fc3946d6fa590dd8047984ed8718a6ffa4ab77 (diff)
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first cut at making a bidirectional 2 port ram for the gpmc data interface
ISE chokes on the unequal size ram
Diffstat (limited to 'usrp2/control_lib')
-rw-r--r--usrp2/control_lib/ram_2port_mixed_width.v44
1 files changed, 44 insertions, 0 deletions
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..3fa43114f
--- /dev/null
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,44 @@
+
+
+module ram_2port_mixed_width
+ #(parameter AWIDTH=9)
+ (input clk16,
+ input en16,
+ input we16,
+ input [10:0] addr16,
+ input [15:0] di16,
+ output reg [15:0] do16,
+
+ input clk32,
+ input en32,
+ input we32,
+ input [9:0] addr32,
+ input [31:0] di32,
+ output reg [31:0] do32);
+
+ reg [31:0] ram [(1<<AWIDTH)-1:0];
+ integer i;
+ initial
+ for(i=0;i<512;i=i+1)
+ ram[i] <= 32'b0;
+
+ always @(posedge clk16)
+ if (en16)
+ begin
+ if (we16)
+ if(addr16[0])
+ ram[addr16[10:1]][15:0] <= di16;
+ else
+ ram[addr16[10:1]][31:16] <= di16;
+ do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+ end
+
+ always @(posedge clk32)
+ if (en32)
+ begin
+ if (we32)
+ ram[addr32] <= di32;
+ do32 <= ram[addr32];
+ end
+
+endmodule // ram_2port_mixed_width